Cool Verification

A few months back I wrote about my initial impressions of Vera.  I recently completed the testbench I started back in September.  Here are some of the things I learned along the way.

Important safety tip - the object_copy() method in Vera does a deep copy of everything, which causes problems if the object you're trying to copy has back references to parent objects (thus potentially causing infinite recursion or severe performance degradation).

I started my verification career using Specman.  As such, I have a pretty good understanding of how to design a verification environment using e and Aspect Oriented Programming (AOP) techniques.  Over the last couple of years I've been building my expertise in strictly OOP based environments such as C++, SystemC, and Vera.  It's been a bit of a struggle, as AOP makes rapid prototyping of a test environment a piece of cake (relatively speaking).  The reason is that AOP allows the creation of cross-cutting concerns that can be applied after the fact to allow the user to modify very specific portions of a data structure.

I mentioned in a previous post that I've been ramping up Vera over the last few weeks.  So far, so good.  One question I had for some of the other guys at Verilab was whether there was a way to easily generate dependencies for a collection of Vera files to use in a Makefile.  As it turns out, Vera has some tricks (which I have yet to fully explore) to help manage which files should be compiled without the user needing to do much at all.  However, our very own Will Partain provided an interesting solution that has the potential to solve the general problem of generating dependencies for any build environment. 

At Verilab we have consultants who are experts in all sorts of languages used in hardware verification.  The big ones at the moment are Specman, Vera, SystemVerilog, and SystemC.  Having experts in all of these languages makes it interesting when we discuss verification issues internally, and allows us to provide advice to clients who are trying to decide which verification language to use on future projects. My languages of choice on my last several projects have been Specman and SystemC.  In preparation for future projects I decided to mix things up a little and ramp up on Vera.