Register Packages and the UVM

Update March 26, 2010: The UVM register package survey is now closed. I am working on compiling the results from 107 valid responses. Stay tuned!

Updated 3/10/2010: Survey link wasn't working from email version of this post. Added a second link.

Many of the Accellera VIP TSC members are in Marlborough, MA this week discussing what features should be part of the first release of the new UVM (Unified Universal Verification Methodology). For those of you who are not familiar, the UVM is meant to be a SystemVerilog library supported by all three vendors. It will be based on the OVM 2.0.3 and will include support for features from other methodologies as we on the committee see fit. 

One of the hot topics during the discussions today was whether the UVM should contain a register package. I believe most of the vendors agree that such a common package is needed. They don't all agree on what form it should take (Cadence, Mentor, or Synopsys version) or when this package should be included in the UVM. For example, is a common register package important enough to delay the release of the UVM 1.0? Should it be based on an existing package or should the vendors attempt to merge their implementations?

Based on these questions, I have a favor to ask of you, my loyal readers. If you have a couple of minutes, please fill out the UVM Register Package Survey (UPDATE 3/10/2010: If that link to a pop-up version of the form doesn't work try this direct link to the survey) and let me know what you think about register packages and the UVM! I'll share the information with the VIP TSC. Also feel free to comment on this post or send me a private email at jl at coolverification dot com.

Some of you may wonder why I ask for company name and email address on the form. These types of surveys have a history of vote packing... I want to make sure I can verify that votes are from real people and not somehow the result of any shenanigans.  If anything looks suspicious, or if I have questions about your comments, I may contact you. I will absolutely not use this info for any other purpose.

Thanks in advance for all your help.


Motivation for the UVM

In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had to be implemented as library on top of verification languages by each user and also in the form of a lack of interoperability of language features between simulators.

To address the missing features there came a verification methodology sent from Synopsys; its name was VMM. The URM from Cadence and the AVM from Mentor came also and later merged to form the OVM, so that through them all engineers might believe in verification libraries.  The libraries did not completely address users’ concerns, but they did serve to validate users’ concerns as valid and worthy of consideration.

The libraries were the solution, and though the solutions were made through them the verification community did not recognize them as the solution because interoperability had not been solved.

Cool Verification 1:1-15 … ;-)

Ahem… As many of you are aware, the Accellera Verification IP Technical Subcommittee (VIP TSC), of which I am a member, is currently working on creating a unified universal verification methodology (UVM) that will be supported by the big three EDA vendors.  Ostensibly the library is being created so that users don’t have to make a (potentially limiting) choice between the OVM and VMM, but can instead use a library that is considered an industry standard. Sounds good, right? I’m going to make the potentially controversial claim that very few semiconductor companies actually care about using an industry standard methodology.

Continue reading "Motivation for the UVM" »