Last Minute Deal on SystemVerilog Training with Cliff Cummings in Beaverton, Oregon, 4/21-24

Those of you who attended SNUG in San Jose know that Cliff Cummings of Sunburst Design was a co-author on our award-winning paper on multi-stream scenarios in the VMM (honorable mention - technical committee award). Cliff (who won Best Paper at SNUG this year) has been a great friend and partner to myself and my colleagues here at Verilab.  As part of our continuing collaborative efforts, I’m planning on sitting in on Cliff’s SystemVerilog course next week in Beaverton, OR. 

Sunburst Design is offering Cool Verification promotional pricing of $2,200 for the 4-day Advanced SystemVerilog for Design & Verification Class or $1,650 for the 3-day Advanced SystemVerilog for Verification class.

To get this pricing, you must register at the web site:

Also, as a special thanks from me for signing up with such short notice, I’m offering to present a new seminar I’m working on as private webinar to the first two registrants using the promotional link above[*].  Here’s the abstract of that material (subject to change):

Choosing a SystemVerilog base class library can be a difficult task, as it is not always clear what features are critical to enhancing productivity. EDA vendors heavily market their solutions but are not able to provide an unbiased viewpoint on the differences between their solutions and others. In this one hour presentation, JL Gray from Verilab will review the major features of the VMM and OVM and describe which features should be given the utmost consideration during the selection process. He will then delve deeper into key topics.

Cliff is also offering special pricing for displaced engineers seeking this or other Sunburst Design training. For details please visit the web site:

If any of you are in the Portland area or can make it up there on short notice, I’d enjoy the opportunity to spend the week with you!

[*] Restrictions apply. Contact me for details.

Verification Now, Coming This October to a Theater Near You!

This year at DAC, Verilab and my colleague David Robinson partnered with SpringSoft to present several seminars on Requirements Based Verification.  I'm pleased to announce that Verilab is working with Certess, Denali, and SpringSoft to present an enhanced and expanded version of the "Requirements Based Verification" session and a new session entitled "Building Flexible and Reusable Testbenches using a Layered Approach to Stimulus Generation" at the Verification Now seminar series in several locations around the world:

  • October 14: Silicon Valley
  • October 21: Austin
  • October 27: Yokohama, Japan
  • October 31: Taipei, Taiwan
  • November 3: Herzliya, Israel

I'll be presenting the material at each location, followed by demos from each of the three sponsoring companies. Interested in attending?  Head on over to the Verification Now website for detailed session and registration info.

Creating a Specman Testbench for the Ethernet Core

Starting this week one of my fellow Verilaber's (is that a word?) from Scotland is in Austin.  The goal is for us to develop a testbench for the Ethernet module using Specman over the next two weeks.  We're going to use the opportunity to allow me to pass along some of my knowledge of the e language and best practices for e testbench development.  The guy I'm working with is no stranger to verification himself. He is a verification expert with years of experience using Vera and (more recently) SystemVerilog.  This is one of the cool things about working at Verilab -- we've got people who have expertise in a wide range of areas.  The best part of working with someone who is learning a new language, especially someone who is an expert in other languages, is that it makes you question some of the things you've been doing by rote without ever truly stopping to wonder why. My personal goal for the week is to use the opportunity to enhance my own testbench development skills and perhaps end up with some verification IP we can use for future training purposes - not just for e but SystemVerilog - especially the assertions portion for starters.

Today we spent time working on the directory structure, patching the Ethernet environment from to remove dependencies on Xilinx and Artisan libraries, and creating shells for the eVCs we'll be developing along the way (Wishbone, MII, and one for the entire Ethernet environment as a whole).  We also drew some block diagrams of the system to make sure we were both on the same page regarding the direction of the testbench.  Tomorrow we'll hopefully be able to continue creating the shells for the eVCs and if we're lucky resolve some of those pesky startup issues that occur on every project.  We've got an extra issue in that I've been trying to get Cadence Incisive and Specman installed under Fedora Core 4.  They mostly work but I'm having some GUI issues with Specview that I haven't been able to resolve ("Connecting to gui...").