SVUG in Austin, Thursday, October 2

Tomorrow (Thursday, October 2) the SystemVerilog User's Group (SVUG) is holding an event in Austin from 2pm to 7pm at Cool River Cafe.  My colleague Jason Sprott, Verilab's VP of Consulting, is presenting, as are Cliff Cummings and others.  Jason, Cliff, and I will all be on a "Stump the Experts" panel moderated by Kelly Larson from MediaTek.  The panel is from 5:20-6pm.  Unfortunately, I'm going to miss the earlier portions of the event due to other commitments but I hope to see those of you who stick around for the panel and the subsequent cocktails and hors d'oeuvres.

Verification Now, Coming This October to a Theater Near You!

This year at DAC, Verilab and my colleague David Robinson partnered with SpringSoft to present several seminars on Requirements Based Verification.  I'm pleased to announce that Verilab is working with Certess, Denali, and SpringSoft to present an enhanced and expanded version of the "Requirements Based Verification" session and a new session entitled "Building Flexible and Reusable Testbenches using a Layered Approach to Stimulus Generation" at the Verification Now seminar series in several locations around the world:

  • October 14: Silicon Valley
  • October 21: Austin
  • October 27: Yokohama, Japan
  • October 31: Taipei, Taiwan
  • November 3: Herzliya, Israel

I'll be presenting the material at each location, followed by demos from each of the three sponsoring companies. Interested in attending?  Head on over to the Verification Now website for detailed session and registration info.

Check Out Comments For 'Goering on Mentor/Cadence VMM Support'

Just wanted to point out to those of you reading via email or RSS feeds that there have been some interesting comments on my Goering on Mentor/Cadence VMM Support post from Steven Bailey (Mentor Graphics), Shalom Bresticker (Intel), David Robinson (Verilab), and Daniel Preda (NoBug).  Also, I received at least one private email chiding me for not including an originally planned reference to 1984 , which I read last month while on vacation (see also this exchange between Gabe Moretti and Grant Martin). 

As always, keep those comments and emails coming!

Goering on Mentor/Cadence VMM Support

Wow... I guess you learn something new every day.  Richard Goering over at SCDSource has just written up a great article on the fact that both Mentor and Cadence now support the VMM.  When I wrote about this last week I'd only heard about the Mentor support.  One of the best parts of the article is Goering's description of a discussion he had with Karen Bartleson of Synopsys:

Bartleson said, however, that Synopsys has no intent to support OVM. "Our goal is to support the Accellera [VIP] standard, so we get some unification. For us to support OVM would mean more confusion in the industry."
Goering continued...
So why is Mentor's support for VMM a good thing for interoperability, while Synopsys support for OVM would sow confusion? "Because VMM has been out there for two to three years in production and OVM was only recently introduced," Bartleson said. "If Mentor supports a more widely accepted, de facto standard, that's good for the industry. If Synopsys supports OVM, which is a new and different implementation, it will fragment things more."

Continue reading "Goering on Mentor/Cadence VMM Support" »

Mentor Releases Customized VMM

A little birdie just gave me a call letting me know that Mentor has released a customized version of the VMM that runs on Questa.  I have not had time to dive in yet, but the associated PDF file that comes with the release takes great pains to describe how the VMM is not compliant with the SystemVerilog spec and why the OVM is better than the "legacy" VMM.  Check out Karen Bartleson's blog for a reaction from Synopsys where she says, "I’d venture to say that despite all the posturing, Mentor’s support of VMM demonstrates the solidity and broad industry acceptance of VMM."

Regardless of the marketing BS from both sides, I'm happy to see a simulator vendor supporting both methodologies, and I hope to see similar moves by Synopsys and Cadence in the near future.

Doxygen Docs for OVM, VMM and Teal/Truss

This post will be short but sweet.  I've recently come across an interesting site, IntelligentDV, that has generated Doxygen documentation for the OVM, VMM and Teal/Truss.  I wasn't able to figure out whether the code required to generate the documentation (i.e. the filter for Doxygen) is on the site or not.  If it was that would certainly be something many people would be interested in.  Anyone with more details about the site and its contents?  If so, I'd appreciate it if you could leave a comment here or send me a mail at jl at coolverification dot com with more info.

OVM World Summit and OVM 2.0

Last Thursday at DAC I participated in a panel discussion at the OVM World Summit.  Unfortunately, I arrived a few minutes late as I went to the Marriott instead of the Sheraton (oops!).  Luckily things had just gotten started and we had an interesting discussion about the benefits of OVM and whether the industry needs a single standard language and methodology for verification. 

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Synopsys Open Sources the VMM

Newsflash - I just got a note from Karen Bartleson at Synopsys letting me know that the VMM is now available for download under an Apache 2.0 open source license!  This is good news - for months the debate between OVM and VMM has been centered around the licensing terms required for each.  Now we can focus on the actual technical differences between the libraries.  I'm also hoping that it won't be long before we see new simulator versions from Cadence, Mentor, and Synopsys that can read both libraries (given the interest each vendor will have in stealing away customers from one another).  This should certainly add some spice to the work of the Accellera VIP TSC!

Also, on another interesting note, I just noticed today that Janick Bergeron of VMM fame has now started his very own blog, Verification Martial Arts.  Welcome to the blogosphere, Janick!  Now we just need to get some folks from Mentor and Cadence blogging and we can have all sorts of fun :-).

On SystemVerilog VIP Interoperability

As I mentioned last week, Verilab is now a member of Accellera.  I've been involved with the newly formed Verification IP Technical Standards Committee.  One of the first objectives of the committee will be to create a Design Objectives Document, otherwise known as a DOD.  Some possible objectives of the committee were presented yesterday during the weekly TSC conference call which spawned an email thread between some of the participants (including myself).  The issue being - what is the scope of the committee?  Is it to come up with a common methodology to be used by all vendors?  Is it to create an API to be used to allow communication between competing methodologies?  Or, is the purpose of the committee more basic than that? 

Continue reading "On SystemVerilog VIP Interoperability" »