Starting this week one of my fellow Verilaber's (is that a word?) from Scotland is in Austin. The goal is for us to develop a testbench for the Opencores.org Ethernet module using Specman over the next two weeks. We're going to use the opportunity to allow me to pass along some of my knowledge of the e language and best practices for e testbench development. The guy I'm working with is no stranger to verification himself. He is a verification expert with years of experience using Vera and (more recently) SystemVerilog. This is one of the cool things about working at Verilab -- we've got people who have expertise in a wide range of areas. The best part of working with someone who is learning a new language, especially someone who is an expert in other languages, is that it makes you question some of the things you've been doing by rote without ever truly stopping to wonder why. My personal goal for the week is to use the opportunity to enhance my own testbench development skills and perhaps end up with some verification IP we can use for future training purposes - not just for e but SystemVerilog - especially the assertions portion for starters.
Today we spent time working on the directory structure, patching the Ethernet environment from Opencores.org to remove dependencies on Xilinx and Artisan libraries, and creating shells for the eVCs we'll be developing along the way (Wishbone, MII, and one for the entire Ethernet environment as a whole). We also drew some block diagrams of the system to make sure we were both on the same page regarding the direction of the testbench. Tomorrow we'll hopefully be able to continue creating the shells for the eVCs and if we're lucky resolve some of those pesky startup issues that occur on every project. We've got an extra issue in that I've been trying to get Cadence Incisive and Specman installed under Fedora Core 4. They mostly work but I'm having some GUI issues with Specview that I haven't been able to resolve ("Connecting to gui...").