Cool Verification

It’s over. After weeks of preparation (on my part, a year on the part of countless others), and a week of staying up late then getting up early, the 46th Annual Design Automation Conference has finally come to a close.  One of the main highlights of the conference was the Synopsys-hosted Conversation Central interactive forum on social media.   I also enjoyed my opportunity to participate on a Pavilion Panel on “Seeking the Holy Grail of Verification Coverage Closure”, to present the new VMM 1.2 updates in the Synopsys theater, and to give a presentation entitled “Zero to Sequences in 30 Minutes” in the OVM World booth.  Special thanks to all of you who spent time talking with me on Monday and Tuesday sharing your thoughts with me on that topic to help me prepare for the panel.  And of course, there was the ever-enjoyable Denali Party (click here for pictures)!

Throughout the conference though, I had a nagging suspicion that I was missing some perspective on where we’ve been as an EDA industry, where we are currently, and where we’re going in the future.  This being only my third DAC, it wasn’t clear to me if anyone was around from the earlier days who would be able to help me fill a gap in my industry knowledge.  After asking around, I quickly realized that I needed to speak with Marie and Pat Pistilli, founders of the aptly named MP Associates and organizers of the very first DAC back in 1964 (and every DAC since).  At the time, DAC was, according to Pat actually called SHARE, which stood for the “Society to Help Avoid Redundant Effort”. 

Pat Pistilli, MP Associates

I was able to arrange a time to meet with Pat on Wednesday evening before the DAC party.  I wasn’t really sure what to expect, and Google wasn’t much help.  So naturally, I asked Pat to tell me about his background and how he ended up founding DAC. In the late 50s Pat was working at Bell Laboratories on a project called “Safeguard”.  (For info on Safeguard, check out the ever-useful Wikipedia. Also, this site dedicated to the Mickelson Safeguard Complex contains a list of references that appear to be relevant).  The idea of the project was to create a computer that could quickly identify which Soviet ICBMs were duds and which were real during a nuclear attack.

We love DAC, but can't follow instructions!
Originally uploaded by brillianthue

This wild mob of DAC lovers was seen roaming around the South Hall Tuesday afternoon at DAC. I tried my very best to corral them to stand *right next to each other* and to *squeeze together*!!! Sadly, my effort failed, so you may get the impression from this photo that they only slightly prefer DAC over the nearest alternative EDA conference ;-).

Update August 12, 2009: Holly and Kathryn have asked me to change the link to the demo from a direct link (that opened the demo but made it appear as if the viewer was me) to a landing page link to a generic Demos on Demand page for Jasper. I've asked for a more direct link but Demos on Demand apparently doesn't make that easy to do.  Look for the demo entitled "Jasper Design Automation: ActiveDesign".  Hopefully the demo will still be visible on that page when you head over there to take a look!

Earlier this year at DVCon, Kathryn Kranen and Holly Stump met with me to discuss Jasper’s new design exploration tool, ActiveDesign.  I ended up meeting with Holly and Rajeev Ranjan, Jasper’s CTO at DAC earlier this week to discuss the topic of my Wednesday panel, “Seeking the Holy Grail of Verification Coverage Closure.”  During that discussion the topic of ActiveDesign came up again, which jogged my memory that I hadn’t posted on the topic after DVCon. 

My favorite part of the Design Automation Conference (or any conference these days) is catching up with old friends. I spent the morning doing just that, making the rounds between the North and South halls of the Moscone Center, with a stop in between to check out the press room.  Of course, more than once I had the embarrassing situation of forgetting the face of an old colleague or client. If you were one of those people, please accept my apologies!

When I first attended DAC in 2007, it was loads of fun. I had nothing to do other than roam around and blog. Last year, I still got to blog, but had some responsibilities in the form of a Birds of a Feather session, an OVM Panel (which I was late for because I went to the wrong hotel) and a presentation on the Myth of SystemVerilog Interoperability.  Somehow, I thought I was busy…  This year, I’ll be involved with several activities on both the technical and social media fronts.  If you have the time, please stop by one of the following events and say hello!

• Synopsys Standards Booth: Mystery Topic[*], Monday 12:35-12:45pm
• Synopsys Conversation Central: So you want to be a blogger? 4:30-5pm M-W
• Synopsys Standards Booth: VMM Demo Station, Tuesday 11a-12p
• Denali Night Live: Tuesday 8p-??? I'll be on stage around 10pm or so... Thank goodness no singing will be involved... right, Dave?!
• OVM World Booth: Zero to Sequences in 30 Minutes, Wednesday 11-11:30am
• Pavilion Panel: Seeking the Holy Grail of Verification Coverage Closure: Wednesday, 2-2:45pm

If you believe I’m supposed to be involved in a public event that is missing from this list, please send me a private email ASAP ;-).

[*] If you want to know what I’ll be talking about, you’ll just have to show up!

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Today I’d like to welcome guest poster Andrew Kahng, General Chair of this year’s Design Automation Conference. I’ve already registered for DAC and am looking forward to an exciting conference. If you are planning on attending please let me know – I’d love to meet up with you in San Francisco! 

Also, as an important note – the early registration deadline is Monday, June 29 (that’s now!). Please register ASAP to get the early-bird discount.

JL

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DAC is a mere five weeks away and, if you check out the technical program (www.dac.com), you’ll see that there are a host of sessions dedicated to verification and test.

While verification is not my area of expertise, a fast skim through the program and specific sessions makes it’s clear to me and anyone in this industry that verification is an ongoing, critical and unmet challenge.

Yes, verification is once again in the spotlight of this year’s DAC as we try to wrestle this challenge. Perhaps the Pavilion panel on the exhibit floor scheduled for Wednesday at 2 p.m. best sums up what we’re facing with the title, “Seeking the Holy Grail of Verification Coverage Closure.” Leading verification experts, including JL Gray, host of this blog Cool Verification, will attempt to determine which solution will lead to the ultimate verification coverage. Another noted verification expert Brian Bailey will moderate what should be a lively and informative discussion.

In addition, you will find sessions on a broad range of verification and test topics too numerous to mention throughout the week –– 16 by my count. They will be held in the IC Design Central Partner Pavilion, the Exhibitor Forum and the User Track, as well as a special session.

Two tutorials are dedicated to the topic of verification. The first, “Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon,” will review state-of-the-art methods for detecting and correcting bugs after the first few silicon prototypes of a design become available. It will be held Friday from 9 a.m. to 5 p.m. “Functional Verification Planning and Management: Navigating from Specification to Functional Closure” will also be held Friday from 9 a.m. to 5 p.m. Its instructors will present leading-edge methods for planning, monitoring and assessing verification progress. Both seem timely and topical.

Of course, the exhibit hall will be filled with more than 200 vendors of all sizes, from industry leaders Cadence, Magma, Mentor and Synopsys to emerging players Atrentra, CoWare, EVE, Jasper, GateRocket, Nusym and Real Intent. For a more complete list of verification vendors, check out the January 15 issue of DACeZine’s directory of verification tools:

www.dac.com/newsletter/shownewsletter.aspx?newsid=69

Register today to learn more about trouncing the verification challenge. I look forward to seeing you in San Francisco.

Andrew Kahng
General Chair
46th Design Automation Conference

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Note: This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today to take advantage of early registration rates, available until Monday, June 29, at: www.dac.com