Yesterday I posted some info about the "HOT Zone" within the DAC party in Austin on Monday evening of next week. As it turns out, I may have a few tickets available (normally would take a $50 donation per ticket). If you're interested in a ticket to the event, send me a note ASAP at jl dot gray at verilab dot com.
As you probably know by now the Design Automation Conference is celebrating its 50th year in Austin, Texas June 2-6. Verilab is excited to be working with Jim Hogan and The Heart of Technology to sponsor the HOT Zone within the DAC party on Monday evening, June 3. See below for more info. If you're in Austin next week, I hope to see you there!
Dear friends and colleagues,The Design Automation Conference is celebrating its 50th year in Austin, Texas. On Monday night, June 3, there is a “Kickin it up in Austin!” 50thAnniversary Celebration at Austin City Limits Live for all DAC attendees.We are proud to be a sponsor of the Heart of Technology’s HOT Zone within the “Kickin it up in Austin!” party. The Heart of Technology (HOT) supports non-profits where all funds raised go directly back into the communities they visit. This year, HOT is helping CASA (Court Appointed Special Advocates) of Travis County, Texas. CASA speaks up for children who’ve been abused or neglected by empowering the community to volunteer as advocates for them in the court system.Donate to CASA and be our guest at the HOT Zone at Austin City Limits LivePlease join HOT’s sponsors and distinguished guests by donating $50.00 or more to CASA: http://www.razoo.com/story/Heart-Of-Technology-Supports-Casa-Of-Travis-CountyYour donation is tax deductible. Contributions go directly to CASA to keep children connected to their siblings, teach skills for life, and provide CASA volunteers.Then, join us in the HOT Zone at DAC’s “Kickin’ it up in Austin!” 50th Anniversary Celebration on June 3 at Austin City Limits Live, for great food, fun, and atmosphere – all while helping CASA of Travis County.On June 3 from 7:30pm-12:00am, present your donation receipt at the CASA kiosk outside Austin City Limits Live. You will receive a wristband to enter the HOT Zone.What’s Sizzling in the HOT ZoneThe HOT Zone is located in the penthouse Jack and Jim Gallery at Austin City Limits Live and features 30 original photographs from the godfather of music photography, Jim Marshall.Here’s what’s happening:
- Private performance by “The Red Headed Stranger”
- Premium drinks including Jack Daniels for which the gallery is named
- Unique food including Texas Treats on a stick and breakfast buffet on a stick
- Photo booth, Airbrush tattoo artist
- Entry into a drawing for a Stratocaster guitar signed by Asleep at the Wheel
- Private balcony seating for main stage performances
- Featured entertainment at the DAC party includes Grammy Award winning artists Asleep at the Wheel, Vista Roads Band, and Texas TerraplanesThe first 100 people to make a donation of $100 or more will receive a special event giveaway!Find out more at www.heartoftechnology.org.Thanks in advance for your donation. We can't wait to party with you at The Hottest Zone at the 50th Anniversary Celebration!HOT Zone sponsors:Atrenta, Ausdia, ChipEstimate.TV, CLK Design Automation, Cronox Group, Display Studios, EDA Consortium, IC Manage, Invarian, MOD Marketing, Nimbic, ProPlus Design Solutions, Si2, Solido, Sonics, Tela Innovations, Uniquify, Verilab, The Waves Studio
As many of you know, DVCon 2013 is next week in San Jose, CA. Verilab will be there in force, including at the UVM tutorial on Monday, poster and paper sessions, a lunch panel, and last, but not least, my 4th Industry Leaders panel, The Road to 1M Design Starts:
How many times have you seen a great idea for a new design effort crushed because the cost of creating it was too great given the probability of getting a good return on investment? It happens at both big companies and small. And, what about the potentially revolutionary ideas that are never even considered because an engineering team or individual would never imagine that a chip would be a possible solution?
Like it or not, developing complex semiconductors comes at an enormous cost. New design flows including use of ESL, Design and Verification IP, Emulation, FPGAs, and the like have all helped contain some of the expansive growth in complexity associated with these efforts. But, is that enough?
What would need to take place in the next 10 years to, on the one hand, reduce the barrier of entry for smaller teams and on the other, dramatically enhance the capabilities of large teams working on the toughest challenges?
The DVCon 2013 Industry Leaders panel will answer the question - what will it take to get to 1M design starts per year?
- Yervant Zorian, Fellow and Chief Architect - Synopsys, Inc.
- Ziv Binyamini,Corporate Vice President, Systems and Software Solutions - Cadence Design Systems, Inc.
- Sunil Shenoy, Corporate Vice President, General Manager, Visual and Parallel Computing Group - Intel Corp.
- John Costello, Vice President, IC Design - Altera Corp.
- Serge Leef, Vice President, New Ventures - Mentor Graphics Corp.
The panel will be held this coming Wednesday, February 27 from 3:30-4:30pm in the Oak/Fir Ballroom at the DoubleTree Hotel in San Jose, CA. I hope to see you there!
The 49th Design Automation Conference kicked off yesterday evening with a reception and a presentation by Gary Smith. One of the themes of Gary's talk was his observation that a phenomenon he termed "multi-platform design" was allowing chips to be designed for approximately $40M, as opposed to the $75M he had predicted last year. Part of the reason for the reduction in cost was, in his view, based on a significantly increasing use of ESL techniques (especially on the modeling and verification side of things).
I spent the day today browsing the show floor and catching up with folks I haven't seen, in some cases, since this time last year. I only got through a small percentage of the show floor, but even so, found some stuff worth seeing. If you have a chance, I'd recommend checking out the following:
- Cadence demo of their new Incisive Debug Analyzer (booth 1930). They demonstrated the ability (not yet released) to step through e testbench code in both time and space after a simulation was completed, just like is currently possible with waveform viewers. It was even possible to step forwards and backwards through code to the point in time where a particular line of code was executed. By the time this is released, it is supposed to also work with SystemVerilog. Definitely a technology to keep an eye on.
- BEEcube's miniBEE (booth 519). From what I saw this looks like it can best be described as a "mini-Palladium" box. Includes a Virtex-6 FPGA, host processor, several different types of I/O ports, and multi-user/network access. This is likely not suitable for folks working on large designs, but could be great for allowing engineers to explore simple design ideas and in general learn about how to build a design prototype.
- Duolog's Sequencer. Duolog (booth 1520) is demoing some new technology to allow users to specify relationships between registers in an executable format. That enables them to create SystemVerilog/UVM code to perform higher level accesses and DUT configuration. The tool is not available for general consumption yet. Instead, they are looking for feedback on how users would expect such a tool to work. If you drop by the Duolog booth, tell Dave Murray and Harry Gries that I sent you, and that I said they promised a pint of Guiness in return for watching their demo ;).
In addition to the above products, I'd also recommend you check out (if you haven't already) the Mentor Verification Academy booth (1514) and website.
It's summertime, and in the EDA world, that can only mean one thing - it's time for the Design Automation Conference. I've been attending DAC since 2007, and for the second time since then DAC is in Anaheim, California. One of the things I find the most difficult about DAC is keeping track of what is going on when, so I thought I'd share what I've come up with so far with all of you. First, here are the events I will personally be participating in:
- 9a-noon: Synopsys Interoperability Booth
- 1:30p - Conversation Central: Verifying the Universe
- I'll be hosting a conversation with Tom Alsop and Hillel Miller about the UVM development effort. The conversation will be streamed live, and you'll be able to call and ask questions if you're not able to attend in person.
- 4:30pm - Moderating the Pavilion Panel: SoC Verification - Are we there yet?
In addition to these events, I've got the following public sessions penciled in on my calendar. Given the complexity of grabbing events from the DAC website and adding them to my calendar, I'm certain I've forgotten an item or two.
For those of you who have not been paying attention, DVCon 2010 starts next week. In a previous post I described several events I'll be involved with except for one very important item. This year I will be moderating the newly dubbed Industry Leaders Panel right after Lip-Bu Tan's keynote address. The panel starts at 3:30pm on Wednesday, February 24.
Why am I hosting the panel this year? As it turns out, David Letterman, John Stewart, and Hugh Jackman were not available (click the link then scroll down and watch the video), so the DVCon steering committee was stuck with me ;-).
This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities. There will, as usual, be a no-holds-barred question and answer period. The panel will be made up of senior managers and directors from some of the world's top semiconductor companies (large, medium, and small), along with the analyst and consultant perspectives.
- Steven Gary - Numetrics Management Systems, Inc.
- John Goodenough - ARM Ltd.
- Sheela Pillai - Advanced Micro Devices, Inc.
- Jim Crocker - Paradigm Works, Inc.
- Victor Melamed - Ambarella
I would very much appreciate and enjoy any public or private comments you would like to share with me about what keeps you up at night on the types of projects you work on. I'm sure those of you approaching tapeout will have a long list! Also, I would like to make the panel as interactive as possible, and will collect any questions you'd like me to ask the panelists on your behalf. Feel free to post comments to this post or mail me at jl at coolverification dot com.
Thanks all, and I look forward to seeing you at DVCon next week!
Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard. As part of that effort, they are soliciting feedback in preparation for an open meeting on February 26 (the Friday after DVCon) where new features will be discussed (see also Brad Pierce's blog article on the topic). Since you'll already be at DVCon (you ARE going to DVCon, right?), it should be easy to take the time to attend the IEEE meeting the next day. Having said that, I'm going to miss the meeting as I'll be on my way to Shanghai to kick off a week of workshops in Asia, but one of my colleagues from Verilab may be attending.
Speaking of DVCon, the early registration deadline is fast approaching. Full conference registration is $485 before January 29. After that, registration goes up to $565. The conference should be outstanding this year, despite the fact that I will be more actively involved than ever before ;-). If you're planning to attend, please stop by and say hello at one of the following events:
- Monday Tutorial: Advanced Verification Techniques Using VMM - I'll be presenting for 45 minutes on the new phasing and factory features in the VMM 1.2.
- Wednesday Industry Leader's Panel: "What Keeps You Up At Night?" (2010-02-17 - I'm moderating this panel - check out my recent post What Keeps You Up at Night for details)
- Thursday session 12.1: Stimulating Scenarios in the OVM and VMM - My favorite methodology topic now as a DVCon paper with my coauthor Scott Roland.
- Thursday Panel: Ever-Onward! Minimizing Verification Time and Effort - Somehow I managed to sneak onto this panel with this distinguished group of panelists. Come by and heckle me for a bit while the votes for best paper are calculated.
As a side note, I'll be traveling extensively in the next couple of months. If you're located in any of the following cities, send me a note and perhaps we can catch up while I'm in town:
- Boston (this week!)
- Mountain View (next week)
- Irvine (next week)
- San Jose (for DVCon)
- Shanghai (first week of March)
Finally, if any of you are reading this and thinking - why isn't JL writing about something more interesting like, say, the UVM, please send me a note letting me know. I've had blog writer's block/burnout for the last few months and could use the encouragement ;-).
In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?” is being held from 11:50-14:00 on Wednesday, November 18, and is made up of four distinguished panelists:
- Harry Foster, Mentor Graphics
- Ziyad Hanna, Jasper Design Automation
- Kevin Harer, Synopsys
- Axel Scherer, Cadence
Those of you who have been reading Cool Verification for awhile will note that I have never really discussed the topic of formal methods on this blog. Truth is, I’ve yet to come across a situation on a project where I needed to use formal to get the job done. My theory is that there are a couple of issues preventing wide-spread adoption of formal tools in a standard verification flow. First, the impression I get is that using formal well requires special expertise to write appropriate properties, partition the design, and interpret the results of the tools. Second, the fact that you need special tools at all. In other words, the fact that I need a separate tool in my flow other than Questasim, VCS, or IUS (not to mention a separate license) makes it difficult for someone to try out formal techniques outside the tool flow of a typical project.
During the panel I plan to ask panelists about just such issues, plus several other questions proposed by thoughtful engineers just like you on the Google Moderator site set up for just this purpose. In fact, I’d like to request your assistance. If you have a question you’d like to see asked of one of the panelists please submit it (or vote on your favorites) via the Google Moderator site or by mailing me directly at jl at coolverification dot com.
I’m also quite interested to hear any stories readers may have with respect to the adoption (or lack thereof) of formal tools in your respective companies and current projects. There are several types of formal tools out there… Any types of tools you’ve had great success with in particular? Or great failures? Does the choice of formal technique heavily depend on the application domain in question? What do you think the EDA vendors need to address in tool functionality/usability in order for you to consider adopting formal more broadly?
And of course, if you’re planning on being in Austin for FMCAD please let me know!
It’s over. After weeks of preparation (on my part, a year on the part of countless others), and a week of staying up late then getting up early, the 46th Annual Design Automation Conference has finally come to a close. One of the main highlights of the conference was the Synopsys-hosted Conversation Central interactive forum on social media. I also enjoyed my opportunity to participate on a Pavilion Panel on “Seeking the Holy Grail of Verification Coverage Closure”, to present the new VMM 1.2 updates in the Synopsys theater, and to give a presentation entitled “Zero to Sequences in 30 Minutes” in the OVM World booth. Special thanks to all of you who spent time talking with me on Monday and Tuesday sharing your thoughts with me on that topic to help me prepare for the panel. And of course, there was the ever-enjoyable Denali Party (click here for pictures)!
Throughout the conference though, I had a nagging suspicion that I was missing some perspective on where we’ve been as an EDA industry, where we are currently, and where we’re going in the future. This being only my third DAC, it wasn’t clear to me if anyone was around from the earlier days who would be able to help me fill a gap in my industry knowledge. After asking around, I quickly realized that I needed to speak with Marie and Pat Pistilli, founders of the aptly named MP Associates and organizers of the very first DAC back in 1964 (and every DAC since). At the time, DAC was, according to Pat actually called SHARE, which stood for the “Society to Help Avoid Redundant Effort”.
I was able to arrange a time to meet with Pat on Wednesday evening before the DAC party. I wasn’t really sure what to expect, and Google wasn’t much help. So naturally, I asked Pat to tell me about his background and how he ended up founding DAC. In the late 50s Pat was working at Bell Laboratories on a project called “Safeguard”. (For info on Safeguard, check out the ever-useful Wikipedia. Also, this site dedicated to the Mickelson Safeguard Complex contains a list of references that appear to be relevant). The idea of the project was to create a computer that could quickly identify which Soviet ICBMs were duds and which were real during a nuclear attack.
Ok, I know what you’re all thinking… “JL, you haven’t even finished writing up DVCon yet and now you’re talking about SNUG?!” Yes, I know. Let’s just say an annoying stream of illnesses have taken their toll on the Gray family (and many other folks as best as I can tell) over the last few weeks. But things seem almost back to normal now and I didn’t want to miss out on an opportunity to let everyone know about my official debut as a conference paper presenter at SNUG San Jose next week.
My Verilab colleagues Jason Sprott and Sumit Dhamanwala, along with Cliff Cummings from Sunburst Design and yours truly authored a paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios”. I’ll be presenting the paper during session MA4: Verification with VMM I on Monday at 11am. Those of you who attended one of the Verification Now 2008 seminars back in the fall will recognize the topic. I discussed the yet to be announced Multi-Stream Scenario additions to the VMM in one of my presentations.
Unlike my Verification Now presentation which compared stimulus in the OVM to the VMM, the SNUG presentation will delve into the topic of Multi-Stream Scenarios in the VMM in more detail. Specifically, I will review the following topics:
- Recap: Single Stream Scenarios
- Complex Stimulus with Multi-Stream Scenarios
- Multi-Stream Scenario Registries (Channel, MSS, and MSSG)
- Single Stream vs. Multi-Stream Scenarios
- Resource Sharing: Grab/Ungrab
- Multi-channel grab
One of the things I hope to touch on is the importance of using the registries when building multi-stream scenarios instead of directly instantiating sub-scenarios, channels, or scenarios from other multi-stream scenario generators (using the generator registry). Those features were added to the MSS solution to allow integrators and test writers to modify the behavior of specific scenarios and scenario generators without having to modify the underlying scenarios themselves.
Another goal is simply to promote the topic of reusable, multi-stream stimulus itself. The VMM has historically supported a flat testbench structure. New features such as MSS, when combined with the vmm_subenv should lead to more reusable and maintainable testbenches.
I’m thrilled to have an opportunity to present at SNUG this year and to meet readers of this blog and my Twitter feed. I will be twittering SNUG using the hash tag #snug, unless someone gives me a good reason to use a different tag. Of course, that begs the question – who will twitter my presentation while I’m presenting? How about this… I will buy the person who Twitters the most insightful comments and/or questions during my presentation a delicious beverage of his/her choice. Any takers?