Cool Verification

Around this time back in 2004, I was discussing the possibility of joining Verilab's just-opened Austin office. My goals were pretty basic - I was unhappy in my job at a local startup, and was looking for a change. I figured I'd get some experience with international travel, and maybe learn a thing or two more about verification. Little did I know then where that journey would take me. 

I made some great friends and learned a ton along the way, but after 9 years, I decided that it was again time to try something new. So back in August, I joined Cadence as a Sr. Architect. In my new role I'll be working across multiple groups and divisions at Cadence, and I may be popping up at various locations around the world as I ramp up on my position and Cadence products and services. I look forward to getting a chance to meet more of you face to face than I may have had an opportunity to do while at Verilab. 

You may be wondering - why Cadence? Did something happen to turn me to the Dark Side of the Force? Possibly. But another explanation is that I was presented with an opportunity to make a positive impact on the EDA industry in collaboration with a group of people I have a lot of respect for. Is everything perfect here? No. But if it was, what would be the point of coming into work every day? 

For my friends at other EDA companies, I hope we can still stay in touch. Things should be easier now. Many of you always harbored deeply-seated suspicions that I was on the Cadence payroll due to my never-ending passion surrounding Specman (except for folks at Cadence, who thought I was on the payroll of some other EDA firm, go figure!). And though those suspicions about Cadence were ill-founded in the past, they are certainly true now. So we all now know where we stand on the matter ;).  

My writing on Cool Verification has been pretty limited over the last couple of years. I hope to keep going with the site, though it's possible my interests may change moving forward. 

There are some significant challenges coming over the months and years ahead. If we're still designing and verifying chips using today's techniques 10-15 years in the future, we'll be in a world of hurt. It's exciting to have a chance to work on defining the future, and I'm looking forward to collaborating with all of you both inside and outside of Cadence to do so.