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Lou Covey Interviews Gary Smith on the $10,000 ASIC

Back in August I wrote a post here on Cool Verification called The $10,000 ASIC about a question I was posing to folks at DAC last summer about whether you could produce a prototype of an advanced chip for a total EDA tool and design/verification IP cost of $10,000.

Lou Covey from New Tech Press has spent the last several months investigating this question and has posted the first in a series of articles and interviews - this time with Gary Smith of Gary Smith EDA:

Gary Smith considers the quest for the $10K chip

In the interview, Gary mentions that it's relatively common to do 2M gate designs to the prototype stage in a couple of months with a budget of just shy of $30K. But he also mentions that it takes upwards of $29M to complete a "very good design". Additionally, investors are more likely to invest in chip design start-ups when the cost involved is closer to $25M.

I'd still like to know if you could reduce the tool and IP costs for the $29M project down to my mythical $10K mark, would it make the chip easier to design and verify, and more palatable to investors?

I'm looking forward to the rest of Lou's series to see what others have to say on the topic!