Delivering Accurate Project Schedules
Interview: Thoughts on Verification

The $10,000 ASIC

I’ve been to DAC each year since 2007. The first time I went to DAC, everything was new and exciting. After a few years, I realized there was a lot that was the same as the year before. To try to get some of the excitement back I decided to set a goal for myself for the conference this year. I would pick a question and spend the conference discussing with as many people as possible. The scenario I chose was:

Imagine you had a team of engineers with expertise in chip architecture, design, and verification available, but a non-recurring tool and IP budget of only $10,000. Under this scenario, is it currently possible to design and create a prototype of the chip using modern techniques? If not today, what would it take to make this possible 10 years from now? And if it was possible to design and create a prototype for $10,000 in tool and IP costs, would that make it easier for you to design chips?

Now, by “prototype” I meant an FPGA prototype that would be suitable for proving to an investor (internal or external) that it would be worth the effort to take the next step and spend a few million dollars going through the process of fabricating the device. And I’m not referring to a “student-grade” design. Think more along the lines of the types of complex ASICs startups today are developing. I asked if reducing tool costs to such a small number would make things easier because it is entirely possible that tool costs are not anywhere close to the gating factor when a company decides to invest in a new chip development effort. For example, if tool costs were only 10–20% of the total, and engineering time was the main gating factor, it might make only a marginal difference if the 10–20% of the cost was reduced to practically zero.

And those of you reading carefully will notice I specified that the budget was non-recurring. In my view, recurring expenses can become a roadblock when attempting to incorporate new technologies into a design and verification flow. Want to try out a new tool that automates the generation of your register design, testbench code, and documentation? Sure, it has a first year cost. But what happens if you need to make occasional updates over the next 3–5 years? You’d need to pay the license fee each year even though you may not be taking full advantage of the tool. This is especially the case for companies where chip design is not their primary raison d’être. These companies may do a single chip in-house, or perhaps outsource the design and verification to a 3rd party. When they bring the design in-house for ongoing maintenance, they now have a problem in that they have yet another tool they need to purchase. So instead of going through all this additional trouble and expense, they choose to either:

  1. Write the tool themselves.
  2. Simply do without the tool.

But doing without the tool is exactly what we’re trying to avoid. As you might expect, I have some thoughts on this topic. And I’ve had several fascinating discussions over the last few months. But I’d be interested to hear from all of you. What do you think? Is the $10,000 ASIC prototype possible today, or is it a pipe dream? Completely useless even if possible? Waste of time even thinking about? Or could such an industrial-grade flow fundamentally change the current, and somewhat staid methods used to verify chips for the last 10–15 years and expand the number of companies who are able to create chips for custom applications?