Cool Verification

My colleague Alex Melikian and I sat down for a chat about verification back in June. The results have been posted on the Verilab blog over the last few weeks. If you happened to miss them, you can check them out here:

Verilab is pleased to introduce “Conversations About Verification”, a monthly publication featuring a discussion on VLSI verification topics. In this inaugural edition, Verilab consultant Alex Melikian discusses first experiences and adoptions of modern verification technologies with JL Gray, Vice President and General Manager, North America of Verilab.

In part 1, JL and Alex discuss about their first experiences involving advanced verification languages and methodologies. They also discuss why and how ASIC/FPGA development centers adopt and integrate Hardware Verification Languages (HVL) and related methodologies into their workflow. In addition, they also discuss some of the impediments as to why others hesitate to make the adoption.

In part 2 of 3 of this conversation, JL and Alex talk over risks/reward involved with adopting an HVL workflow, as well as the diverging perspectives from management and engineers in a company. Also, they discuss the state of HVL technologies today and what might evolve from it next.

In part 3, JL and Alex discuss some of the methodologies, outside of, but complimentary to HVL technologies, such as continuous integration. Typical mistakes and growing pains of adopting HVL methodologies are also reviewed. Finally, JL discusses about his verification blog, along with the various discussions and debates it has generated.

I’ve been to DAC each year since 2007. The first time I went to DAC, everything was new and exciting. After a few years, I realized there was a lot that was the same as the year before. To try to get some of the excitement back I decided to set a goal for myself for the conference this year. I would pick a question and spend the conference discussing with as many people as possible. The scenario I chose was:

Imagine you had a team of engineers with expertise in chip architecture, design, and verification available, but a non-recurring tool and IP budget of only $10,000. Under this scenario, is it currently possible to design and create a prototype of the chip using modern techniques? If not today, what would it take to make this possible 10 years from now? And if it was possible to design and create a prototype for $10,000 in tool and IP costs, would that make it easier for you to design chips?

Now, by “prototype” I meant an FPGA prototype that would be suitable for proving to an investor (internal or external) that it would be worth the effort to take the next step and spend a few million dollars going through the process of fabricating the device. And I’m not referring to a “student-grade” design. Think more along the lines of the types of complex ASICs startups today are developing. I asked if reducing tool costs to such a small number would make things easier because it is entirely possible that tool costs are not anywhere close to the gating factor when a company decides to invest in a new chip development effort. For example, if tool costs were only 10–20% of the total, and engineering time was the main gating factor, it might make only a marginal difference if the 10–20% of the cost was reduced to practically zero.