UVM Drivers and Monitors
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49th DAC: Day 1 Highlights

The 49th Design Automation Conference kicked off yesterday evening with a reception and a presentation by Gary Smith. One of the themes of Gary's talk was his observation that a phenomenon he termed "multi-platform design" was allowing chips to be designed for approximately $40M, as opposed to the $75M he had predicted last year. Part of the reason for the reduction in cost was, in his view, based on a significantly increasing use of ESL techniques (especially on the modeling and verification side of things). 

I spent the day today browsing the show floor and catching up with folks I haven't seen, in some cases, since this time last year. I only got through a small percentage of the show floor, but even so, found some stuff worth seeing. If you have a chance, I'd recommend checking out the following: 

  • Cadence demo of their new Incisive Debug Analyzer (booth 1930). They demonstrated the ability (not yet released) to step through e testbench code in both time and space after a simulation was completed, just like is currently possible with waveform viewers. It was even possible to step forwards and backwards through code to the point in time where a particular line of code was executed. By the time this is released, it is supposed to also work with SystemVerilog. Definitely a technology to keep an eye on.
  • BEEcube's miniBEE (booth 519). From what I saw this looks like it can best be described as a "mini-Palladium" box. Includes a Virtex-6 FPGA, host processor, several different types of I/O ports, and multi-user/network access. This is likely not suitable for folks working on large designs, but could be great for allowing engineers to explore simple design ideas and in general learn about how to build a design prototype. 
  • Duolog's Sequencer. Duolog (booth 1520) is demoing some new technology to allow users to specify relationships between registers in an executable format. That enables them to create SystemVerilog/UVM code to perform higher level accesses and DUT configuration. The tool is not available for general consumption yet. Instead, they are looking for feedback on how users would expect such a tool to work. If you drop by the Duolog booth, tell Dave Murray and Harry Gries that I sent you, and that I said they promised a pint of Guiness in return for watching their demo ;).

In addition to the above products, I'd also recommend you check out (if you haven't already) the Mentor Verification Academy booth (1514) and website