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Virtual Panel Discussion: System Level Verification on Thursday, November 18

Just wanted to give everyone a heads up that I'll be participating in an online panel discussion as part of the EE Times System-on-a-chip 2.0 virtual conference next Thursday, November 18. 

Information about the panel is below. I look forward to "seeing" you there!

Time: 4:30 pm - 5:30 pm EASTERN TIME

Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. There is a tremendous variety of software and hardware-assisted verification technologies available, but which will be the most effective for a particular project? What special verification tools and flows are available for ASIC and FPGA-based SoCs? Can point tools address any "EDA holes" in the large ASIC- and FPGA-based SoC design flows? Architecture-related verification, RTL debug, formal verification, and hardware-assisted verification technologies will all be considered in this session.

Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive

Panelists:

  • JL Gray, Vice President, Verilab, Inc.
  • Jack Donovan, Founder, SystematIC Design
  • Brian Bailey, President, Brian Bailey Consulting
  • Rajeev K. Ranjan, Chief Technology Officer, Jasper Design Automation