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UVM-EA Release Details

As I mentioned earlier in the week, the Universal Verification Methodology – Early Adopter release (UVM-EA) was announced on Monday and can be downloaded from the Accellera website. The process for putting together this release has been both exhilarating and frustrating, and it has highlighted (at least for me) the potentially transformative impact wide adoption of this library could have on the industry. Many users, from those with the most basic skills to those with the most advanced, have held off selecting a commercially available verification methodology for SystemVerilog. Initially, this may have been because they did not want to be locked in to a specific SystemVerilog simulator, though until recently (and, to be honest, still somewhat today), it was extremely difficult to write code that compiled on all three major simulators regardless of methodology. Some felt the VMM and OVM were too complex; others felt the libraries were ill-suited to their particular needs. 

Though I doubt anyone is going to stop what they’re doing and adopt the UVM mid-project, I believe engineers starting new verification efforts will take a serious look at the UVM.

Continue reading "UVM-EA Release Details" »

Video: UVM Register Package Survey Results

I gave a presentation earlier today on the UVM register package survey results. I decided to record a video of the presentation for your viewing pleasure. One thing I didn't address in the video is a question I've received a few times about how many companies (as opposed to individuals) responded for each package. The biggest responses were for Synopsys and Cadence packages. 36 companies responded that they used the Synopsys SystemVerilog register package. 10 companies responded that they use the Cadence package. Remember - these numbers are influenced by package usage and by how much vendors promoted my survey to their customers. So I make no claims (nor should you) about register package market share from the answers for Question 1 in the survey.

As always, comments welcome! And just in case, here is the link to the video if it doesn't show up below.

Quick Video: Signing Up to Participate in the Accellera UVM Effort

I've been looking into doing some online videos recently, and thought it would be fun as a test to show how simple it is for non-members to participate in the Accellera Verification IP technical subcommittee UVM development effort.

Signing Up to Participate in the Accellera UVM Effort (direct link)

Keep in mind this is the first time I've created a web video... constructive comments or questions are very much appreciated!