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UVM Register Package Survey Results

A little over a month ago I sent out a request for your feedback on the possibility of adding a standardized register package to the UVM. Over the next 10 days I received 119 entries, 107 of which I consider valid (meaning they included an apparently real name and company email address, and did not appear to be duplicate submissions). Those 107 entries came from 63 different companies. The goal of the survey was to allow me to provide better input into the Accellera Verification IP TSC on whether a register package should be part of the UVM at some point.  The survey included the following questions:

  1. Which SystemVerilog register package do you currently use?
    • Cadence
    • Mentor
    • Synopsys
    • Multiple
    • Home grown
    • None
    • Other 
  2. How important is it that the UVM contain a register package?
    • Critical - we won't adopt the UVM without it
    • Important - should be in the first release, but would be satisfied with the UVM even without this feature
    • Low - Happy with whatever the TSC comes up with
    • Don't care at all 
  3. Would you be willing to delay the release of the UVM so that it could include a register package?
    • Yes
    • No
    • Don't Care 

Many respondents also included comments. I’m going through those comments and will share them once I have a chance to scrub them of any personally identifying information. So, without further ado, here are the results. Values are listed as the number of responses for each answer.

Continue reading "UVM Register Package Survey Results" »

Surprise, surprise... the "UVM-EA Kit" is already out of date!

Just to update everyone on the warning I posted last week. As expected, the current state of the Unified Universal Verification Methodolgy (UVM) library has changed such that the UVM-EA "kit" that was announced last week is already out of date. Actually, to be precise, the kit was never "in date", if that's even a valid phrase. But things have moved forward even in the last few days. If you're looking for information on the UVM, my recommendation is to be patient. Things are changing on a weekly basis, and the only way to stay on top of things for now is to start becoming involved with the Accellera VIP TSC. If you'd like to find out how to participate, please let me know and I'll fill you in on all the gory details.

EDA Vendors: Do More With Less

This post is for all of those lonely EDA vendors out there, wondering whether or how they're going to attract customers at the upcoming Design Automation Conference. You may have heard of Xuropa. Xuropa started out a couple of years ago focused on two things - creating an EDA social community and a related capability for vendors to showcase their products. Recently, they appear to have dropped the social networking aspect and really focused on enabling vendors to demonstrate their products via on-demand access to vendor "labs". The labs are basically controlled environments where users can actually run tools with all of the relevant files, licenses, and configuration already set up, without having to actually install anything on their own servers. 

How is this related to DAC?  As you may have guessed by now, Xuropa's online labs could be used to demonstrate your tools to customers on the DAC floor with only a network-connected laptop. Any heavy lifting required to run tools can be done on the Xuropa servers. Xuropa is giving away a free Xuropa Cloud Application Server and Collaboration Environment to the person with the best tip on how to "do more with less". If you're an EDA vendor planning to attend DAC, you'll want to check out Xuropa's "Do More With Less" contest for information on how to win.

Warning: The UVM "Early Adopter" (UVM-EA) release does not exist yet!

Some of you may have seen an announcement on Friday describing an early adopter kit of the UVM "based on the Accellera Verification IP Technical Subcommittee (VIP-TSC) decisions to date". Being a member of the Accellera VIP-TSC myself, I can assure you that the detailed technical contents of the purported "EA" release are still in flux. Anyone announcing such a release, even as a "kit" provided to allow users "to confidently start the process verifying your OVM products offerings in an UVM environment" is at best, misinformed about the current state of the UVM development effort and at worst endeavoring to hamper progress of the UVM. 

Consider yourselves warned.

One other point worth mentioning is that, at present, the UVM will be based on the OVM 2.1.1 code base but will only be reasonably backward compatible[*] with the OVM 2.0.3. Of course, this is subject to change based on future committee votes. I wish I didn't have to say this, but anyone telling you otherwise is probably trying to sell you something... 

For those of you who submitted responses to my register package survey, I've tabulated the results but am still working on anonymizing comments so I can share the details with Cool Verification readers and the VIP-TSC. Stay tuned!

[*] Updated since the original post - the UVM will not actually be directly backward compatible with any version of the OVM. Names of classes will be changed, some implementation details may be changed or deprecated, etc. Best to wait for official word from Accellera on what the first release of the library will look like.