A little over a month ago I sent out a request for your feedback on the possibility of adding a standardized register package to the UVM. Over the next 10 days I received 119 entries, 107 of which I consider valid (meaning they included an apparently real name and company email address, and did not appear to be duplicate submissions). Those 107 entries came from 63 different companies. The goal of the survey was to allow me to provide better input into the Accellera Verification IP TSC on whether a register package should be part of the UVM at some point. The survey included the following questions:
- Which SystemVerilog register package do you currently use?
- Home grown
- Critical - we won't adopt the UVM without it
- Important - should be in the first release, but would be satisfied with the UVM even without this feature
- Low - Happy with whatever the TSC comes up with
- Don't care at all
- Don't Care
Many respondents also included comments. I’m going through those comments and will share them once I have a chance to scrub them of any personally identifying information. So, without further ado, here are the results. Values are listed as the number of responses for each answer.