Cool Verification

For those of you who have not been paying attention, DVCon 2010 starts next week. In a previous post I described several events I'll be involved with except for one very important item.  This year I will be moderating the newly dubbed Industry Leaders Panel right after Lip-Bu Tan's keynote address.  The panel starts at 3:30pm on Wednesday, February 24.

Why am I hosting the panel this year? As it turns out, David Letterman, John Stewart, and Hugh Jackman were not available (click the link then scroll down and watch the video), so the DVCon steering committee was stuck with me ;-).

This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities. There will, as usual, be a no-holds-barred question and answer period. The panel will be made up of senior managers and directors from some of the world's top semiconductor companies (large, medium, and small), along with the analyst and consultant perspectives.

• Steven Gary - Numetrics Management Systems, Inc.
• John Goodenough - ARM Ltd.
• Sheela Pillai - Advanced Micro Devices, Inc.
• Jim Crocker - Paradigm Works, Inc.
• Victor Melamed - Ambarella

I would very much appreciate and enjoy any public or private comments you would like to share with me about what keeps you up at night on the types of projects you work on. I'm sure those of you approaching tapeout will have a long list! Also, I would like to make the panel as interactive as possible, and will collect any questions you'd like me to ask the panelists on your behalf. Feel free to post comments to this post or mail me at jl at coolverification dot com.

Thanks all, and I look forward to seeing you at DVCon next week!

In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had to be implemented as library on top of verification languages by each user and also in the form of a lack of interoperability of language features between simulators.

To address the missing features there came a verification methodology sent from Synopsys; its name was VMM. The URM from Cadence and the AVM from Mentor came also and later merged to form the OVM, so that through them all engineers might believe in verification libraries.  The libraries did not completely address users’ concerns, but they did serve to validate users’ concerns as valid and worthy of consideration.

The libraries were the solution, and though the solutions were made through them the verification community did not recognize them as the solution because interoperability had not been solved.

Cool Verification 1:1-15 … ;-)

Ahem… As many of you are aware, the Accellera Verification IP Technical Subcommittee (VIP TSC), of which I am a member, is currently working on creating a unified universal verification methodology (UVM) that will be supported by the big three EDA vendors.  Ostensibly the library is being created so that users don’t have to make a (potentially limiting) choice between the OVM and VMM, but can instead use a library that is considered an industry standard. Sounds good, right? I’m going to make the potentially controversial claim that very few semiconductor companies actually care about using an industry standard methodology.