Previous month:
October 2009
Next month:
February 2010

SystemVerilog 2012, DVCon 2010, and Travel

Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard.  As part of that effort, they are soliciting feedback in preparation for an open meeting on February 26 (the Friday after DVCon) where new features will be discussed (see also Brad Pierce's blog article on the topic).  Since you'll already be at DVCon (you ARE going to DVCon, right?), it should be easy to take the time to attend the IEEE meeting the next day.  Having said that, I'm going to miss the meeting as I'll be on my way to Shanghai to kick off a week of workshops in Asia, but one of my colleagues from Verilab may be attending.  

Speaking of DVCon, the early registration deadline is fast approaching.  Full conference registration is $485 before January 29.  After that, registration goes up to $565. The conference should be outstanding this year, despite the fact that I will be more actively involved than ever before ;-).  If you're planning to attend, please stop by and say hello at one of the following events:

  • Monday Tutorial: Advanced Verification Techniques Using VMM - I'll be presenting for 45 minutes on the new phasing and factory features in the VMM 1.2.
  • Wednesday Industry Leader's Panel: "What Keeps You Up At Night?" (2010-02-17 - I'm moderating this panel - check out my recent post What Keeps You Up at Night for details)
  • Thursday session 12.1: Stimulating Scenarios in the OVM and VMM - My favorite methodology topic now as a DVCon paper with my coauthor Scott Roland.
  • Thursday Panel: Ever-Onward! Minimizing Verification Time and Effort - Somehow I managed to sneak onto this panel with this distinguished group of panelists. Come by and heckle me for a bit while the votes for best paper are calculated.

As a side note, I'll be traveling extensively in the next couple of months.  If you're located in any of the following cities, send me a note and perhaps we can catch up while I'm in town:

  • Boston (this week!)
  • Mountain View (next week)
  • Irvine (next week)
  • San Jose (for DVCon)
  • Shanghai (first week of March)
  • Taipei/Hsinchu
  • Tokyo

Finally, if any of you are reading this and thinking - why isn't JL writing about something more interesting like, say, the UVM, please send me a note letting me know. I've had blog writer's block/burnout for the last few months and could use the encouragement ;-).


As a potential user of the UVM, would you like to be able to view active development branches within the live UVM repository, or should this information be hidden until official releases are made?


Yet another Accellera call about the Unified Verification Methodology (UVM) is underway. My takeaway? Both EDA and user companies put such a premium on secrecy that a truly open development process is simply not possible. Based on its current trajectory, the EDA vendors appear to have the desire to have a preview of potential innovations before they may be shared with the Accellera committee. Why? Because the only people capable of discussing certain aspects, such as **log files** of EDA vendor tools are the vendors themselves.