My favorite part of the Design Automation Conference (or any conference these days) is catching up with old friends. I spent the morning doing just that, making the rounds between the North and South halls of the Moscone Center, with a stop in between to check out the press room. Of course, more than once I had the embarrassing situation of forgetting the face of an old colleague or client. If you were one of those people, please accept my apologies!
I also had the opportunity to check out the new Conversation Central room at the Synopsys Booth. I was able to catch parts of Karen Bartleson’s “Twitter for Newbies”, Harry Gries’ “Job Search: How Social Media Can Help Job Seekers & Employers”, and John Cooley’s “The Evolution of ESNUG & DeepChip”.
Check out additional pics from the Conversation Central room on Flickr. My own afternoon session on “So, you want to be a blogger” overlapped with the CEO panel. That won’t be the case tomorrow, so please stop by if you have a chance!
Around lunchtime I presented on the new features in the to-be-announced VMM 1.2 in the Synopsys Interoperability Theater. Some of the highlights:
- TLM 2.0
- Enhanced Phasing
- Test Concatenation
- And more!
I believe users of the VMM will be pleased with these latest updates. (Full disclosure: I’ve worked with Synopsys to review portions of the 1.2 release). If you’d like to learn more please stop by the VMM Demo Booth Tuesday (11am-noon).
One of the highlights of my day was getting a chance to meet Pat and Marie Pistilli of MP Associates, who were involved in the very first DAC. I’m hoping to chat with them further tomorrow (and at the very least, get a photo)!
I wrapped up my evening by attending the Synopsys University Reception. I missed most of the presentations, but did catch one from Professor Kaushik Roy from my alma mater Purdue University. I enjoyed hearing Professor Roy, but was left with the continued impression that most professors of Electrical and Computer engineering focus on backend issues or perhaps formal verification, to the exclusion of pretty much anything related to pre-silicon verification. I would love to hear about any university research being done in areas of interest to verification engineers.