Cool Verification

We love DAC, but can't follow instructions!

We love DAC, but can't follow instructions!
Originally uploaded by brillianthue

This wild mob of DAC lovers was seen roaming around the South Hall Tuesday afternoon at DAC. I tried my very best to corral them to stand *right next to each other* and to *squeeze together*!!! Sadly, my effort failed, so you may get the impression from this photo that they only slightly prefer DAC over the nearest alternative EDA conference ;-).

Thoughts on Jasper ActiveDesign?

Update August 12, 2009: Holly and Kathryn have asked me to change the link to the demo from a direct link (that opened the demo but made it appear as if the viewer was me) to a landing page link to a generic Demos on Demand page for Jasper. I've asked for a more direct link but Demos on Demand apparently doesn't make that easy to do.  Look for the demo entitled "Jasper Design Automation: ActiveDesign".  Hopefully the demo will still be visible on that page when you head over there to take a look!

Earlier this year at DVCon, Kathryn Kranen and Holly Stump met with me to discuss Jasper’s new design exploration tool, ActiveDesign.  I ended up meeting with Holly and Rajeev Ranjan, Jasper’s CTO at DAC earlier this week to discuss the topic of my Wednesday panel, “Seeking the Holy Grail of Verification Coverage Closure.”  During that discussion the topic of ActiveDesign came up again, which jogged my memory that I hadn’t posted on the topic after DVCon. 

Denali DAC 2009 Party Pictures Posted!

Ted Vucurevich
Originally uploaded by brillianthue

Just a quick note that I've posted my photos from the Denali party last night on Flickr. Let me know what you think! 

Also, congratulations to Karen Bartleson of Synopsys for winning the EDA's Next Top Blogger competition!

Something Old, Something New: Monday at DAC

My favorite part of the Design Automation Conference (or any conference these days) is catching up with old friends. I spent the morning doing just that, making the rounds between the North and South halls of the Moscone Center, with a stop in between to check out the press room.  Of course, more than once I had the embarrassing situation of forgetting the face of an old colleague or client. If you were one of those people, please accept my apologies!

DAC 2009 Presentation Schedule: JL Gray

When I first attended DAC in 2007, it was loads of fun. I had nothing to do other than roam around and blog. Last year, I still got to blog, but had some responsibilities in the form of a Birds of a Feather session, an OVM Panel (which I was late for because I went to the wrong hotel) and a presentation on the Myth of SystemVerilog Interoperability.  Somehow, I thought I was busy…  This year, I’ll be involved with several activities on both the technical and social media fronts.  If you have the time, please stop by one of the following events and say hello!

• Synopsys Standards Booth: Mystery Topic[*], Monday 12:35-12:45pm
• Synopsys Conversation Central: So you want to be a blogger? 4:30-5pm M-W
• Synopsys Standards Booth: VMM Demo Station, Tuesday 11a-12p
• Denali Night Live: Tuesday 8p-??? I'll be on stage around 10pm or so... Thank goodness no singing will be involved... right, Dave?!
• OVM World Booth: Zero to Sequences in 30 Minutes, Wednesday 11-11:30am
• Pavilion Panel: Seeking the Holy Grail of Verification Coverage Closure: Wednesday, 2-2:45pm

If you believe I’m supposed to be involved in a public event that is missing from this list, please send me a private email ASAP ;-).

[*] If you want to know what I’ll be talking about, you’ll just have to show up!

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Vote for EDA’s Next Top Blogger

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Do You Know Your Project's 'Truck Factor'?

Yesterday I presented another full-day workshop on verification planning - this time in Denver. During these workshops I discuss two major topics. First, we discuss a framework to help you understand your design. We break up a design into "efficient" subsections, and then search for "operations" that make up each of these subsections. Second, once you have an understanding of your design, we discuss the concept of a Failure Mode and Effects Analysis (FMEA). An FMEA is a cross-functional meeting used to brainstorm possible faults and failures. We use that information to come up with a verification plan.

ovm_transaction vs. ovm_sequence_item

I've been having a discussion on Twitter over the last couple of days that the rest of you may find interesting. The question I posed was:

"Can someone give me a reason why I would ever use ovm_transaction instead of ovm_sequence_item? I can't think of any..."

Paul Marriott suggested you should use ovm_transaction to signify intent not to use the data item in a sequence. Dallas McNally suggested the OVM should have used composition instead of inheritance to add the sequence functionality to an OVM transaction.  What do I think? 

As best as I can tell there is absolutely no compelling reason to ever use ovm_transaction. If you use that class for your data item, it can never be used as a sequence. You might think, "Hey, no one would want to use this packet data class in a sequence." But a year or two later (or a group or two later) someone might want exactly that, but they would be prevented from doing so because the class was based on ovm_transaction.  If you have control of the code that's easy to fix, but if not (think VIP) you are stuck.

The only things that are added are additional functions to deal with sequences. It's not clear to me that there would be any performance penalty at all. If I really don't want something to be a sequence item, I would just derive it directly from ovm_object. For example, Paul suggested on Twitter that a configuration value should be an ovm_transaction, not an ovm_sequence_item. That sounds bogus to me - it should just be based on ovm_object if it really is just a generic data structure!

However, I'm happy for someone to prove me wrong.  Anyone want to take a shot? :-)

Also, remember to vote for EDA's Next Top Blogger!

SystemVerilog Syntax Highlighting for PowerPoint

It's late... very late... and I'm working on slides for one of my DAC presentations, "Zero to Sequences in 30 Minutes". My slides contain source code, and the code is not easy to read. I thought, "Wouldn't it be great if I could colorize the code?" Luckily, Sean over at IntelligentDV wrote a blog article on exactly this topic last year. However, did I mention it's very late? So the idea of screwing around with a new editor and installing syntax files didn't really appeal to me. However, after reading that article plus some follow-up Google searching, I realized if I could get vim to save its syntax-highlighted output as HTML I could copy that directly into PowerPoint. But how? 

This blog post by "Automatthias" describes one solution. From VIM, run the following command in a syntax-highlighted buffer:

:runtime! syntax/2html.vim

This saves the current buffer with a .html extension. Open that extension in your favorite browser and you can copy the colorized text directly into PowerPoint! The only catch - make sure you select "Keep Source Formatting". Otherwise, the colors will be lost.

By the way, as many of you are aware, Denali is holding a competition to determine "EDA's Next Top Blogger". There are several excellent bloggers in contention, including your's truly.  I've had the pleasure of meeting and working with some of them, including Karen Bartleson, Harry Gries, and John Busco (who I believe is the only one of the entire group of contestants who's been blogging longer than me), and let me tell you, I'm honored to be in such good company! If you've enjoyed reading Cool Verification over the last 4 years (yes, it's been that long!) please head over to the Denali Night Live site and cast your vote!