Previous month:
April 2009
Next month:
July 2009

Verification in the Spotlight (or Hot Lights) of DAC

Today I’d like to welcome guest poster Andrew Kahng, General Chair of this year’s Design Automation Conference. I’ve already registered for DAC and am looking forward to an exciting conference. If you are planning on attending please let me know – I’d love to meet up with you in San Francisco! 

Also, as an important note – the early registration deadline is Monday, June 29 (that’s now!). Please register ASAP to get the early-bird discount.

JL

-------------------------------------------------------------------

andrew_kahng DAC is a mere five weeks away and, if you check out the technical program (www.dac.com), you’ll see that there are a host of sessions dedicated to verification and test.

While verification is not my area of expertise, a fast skim through the program and specific sessions makes it’s clear to me and anyone in this industry that verification is an ongoing, critical and unmet challenge.

Yes, verification is once again in the spotlight of this year’s DAC as we try to wrestle this challenge. Perhaps the Pavilion panel on the exhibit floor scheduled for Wednesday at 2 p.m. best sums up what we’re facing with the title, “Seeking the Holy Grail of Verification Coverage Closure.” Leading verification experts, including JL Gray, host of this blog Cool Verification, will attempt to determine which solution will lead to the ultimate verification coverage. Another noted verification expert Brian Bailey will moderate what should be a lively and informative discussion.

In addition, you will find sessions on a broad range of verification and test topics too numerous to mention throughout the week –– 16 by my count. They will be held in the IC Design Central Partner Pavilion, the Exhibitor Forum and the User Track, as well as a special session.

Two tutorials are dedicated to the topic of verification. The first, “Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon,” will review state-of-the-art methods for detecting and correcting bugs after the first few silicon prototypes of a design become available. It will be held Friday from 9 a.m. to 5 p.m. “Functional Verification Planning and Management: Navigating from Specification to Functional Closure” will also be held Friday from 9 a.m. to 5 p.m. Its instructors will present leading-edge methods for planning, monitoring and assessing verification progress. Both seem timely and topical.

Of course, the exhibit hall will be filled with more than 200 vendors of all sizes, from industry leaders Cadence, Magma, Mentor and Synopsys to emerging players Atrentra, CoWare, EVE, Jasper, GateRocket, Nusym and Real Intent. For a more complete list of verification vendors, check out the January 15 issue of DACeZine’s directory of verification tools:

www.dac.com/newsletter/shownewsletter.aspx?newsid=69

Register today to learn more about trouncing the verification challenge. I look forward to seeing you in San Francisco.

Andrew Kahng
General Chair
46th Design Automation Conference

###

Note: This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today to take advantage of early registration rates, available until Monday, June 29, at: www.dac.com