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IEEE 1647 Call For Participation

April 27, 2009

Those of you who have been reading Cool Verification since the early days will know that I'm a big proponent of the e language.  The IEEE 1647 working group is looking for volunteers to help develop the next version of the e-language standard.  What follows is a letter from Serrie Chapman, a member of the IEEE 1647 committee.  If you have any questions please let me know and I'll pass them along to the appropriate committee members.


Individuals interested in functional verification languages are hereby invited to take part in the 1647 working group effort. This effort is aimed at standardizing the e functional verification language. The e language has been evolving since it's introduction in 1996, and is used today by a large community of industrial and academic users.

We are currently working towards the P1647-2010 revision of the standard and the following widely used language features are part of this effort:
  • Define-As-Computed
  • Interface Ports
  • Named Constraints
  • Parameterized Types
  • Real Data Type
  • Temporal Coverage
  • Type Constraints
Anybody with any interest in the e language could effect changes in the upcoming revision which could be of benefit to you. Consequently, I'm calling on new participants to help push this language forward by joining the IEEE Working Group for the e language yourself, or/and inviting any interested parties.

The good news is that it's very easy to participate: simply dial-in to an hour-long conference call once a month via a toll-free number setup for your home country. You can dive in and contribute to the discussion, or sit back and quietly monitor the group's progress.

Alternatively, a single message posted to the IEEE 1647 working group email reflector on a topic recorded in the minutes of the previous meeting is sufficient to qualify the author as attending the associated meeting. Either way, you will be able to ensure you & your company's needs will be captured in the standard.

The next working group meeting will be posted on the website and I welcome you or/and a colleague to dial-in to get a feel for the Group. The agenda, along with a list of world-wide toll free dial-in numbers, is posted here: http://ieee1647.org/agenda.html

If you want to join, please submit your details on http://ieee1647.org/join.html

And please let me know if you have any further questions.

Warm Regards,

Serrie Chapman
Member, IEEE 1647 Working Group

Posted at 03:30 PM in Specman | | Comments (6)

Last Minute Deal on SystemVerilog Training with Cliff Cummings in Beaverton, Oregon, 4/21-24

April 18, 2009

Those of you who attended SNUG in San Jose know that Cliff Cummings of Sunburst Design was a co-author on our award-winning paper on multi-stream scenarios in the VMM (honorable mention - technical committee award). Cliff (who won Best Paper at SNUG this year) has been a great friend and partner to myself and my colleagues here at Verilab.  As part of our continuing collaborative efforts, I’m planning on sitting in on Cliff’s SystemVerilog course next week in Beaverton, OR. 

Sunburst Design is offering Cool Verification promotional pricing of $2,200 for the 4-day Advanced SystemVerilog for Design & Verification Class or $1,650 for the 3-day Advanced SystemVerilog for Verification class.

To get this pricing, you must register at the web site:
http://www.sunburst-design.com/systemverilog_training/PROMO/

Also, as a special thanks from me for signing up with such short notice, I’m offering to present a new seminar I’m working on as private webinar to the first two registrants using the promotional link above[*].  Here’s the abstract of that material (subject to change):

Choosing a SystemVerilog base class library can be a difficult task, as it is not always clear what features are critical to enhancing productivity. EDA vendors heavily market their solutions but are not able to provide an unbiased viewpoint on the differences between their solutions and others. In this one hour presentation, JL Gray from Verilab will review the major features of the VMM and OVM and describe which features should be given the utmost consideration during the selection process. He will then delve deeper into key topics.

Cliff is also offering special pricing for displaced engineers seeking this or other Sunburst Design training. For details please visit the web site:
http://www.sunburst-design.com/DISPLACED/

If any of you are in the Portland area or can make it up there on short notice, I’d enjoy the opportunity to spend the week with you!

[*] Restrictions apply. Contact me for details.

Posted at 06:32 PM in SystemVerilog, Training | | Comments (0)