It’s only Monday and already there have been several interesting press releases in the wonderful wide world of EDA. Here is a breakdown of what I’ve heard about so far.
This is, IMHO, the biggest news of the day. For full disclosure, SpringSoft and Certess were both sponsors of the Verification Now seminar series I presented at last fall. This acquisition means that SpringSoft will now have a new and unique product to add to their portfolio. I would also suspect there could be opportunities for integration between the Certess Functional Qualification technology and the debug technology in Verdi. Journalist Chris Edwards made the following comment in response to the news this morning on Twitter:
@jlgray Springsoft's portfolio is a bit of a smorgasbord but in this climate, is one of the few EDA cos that could do comparatively well
I guess only time will tell. I know the folks at Certess are passionate about their technology and I’m sure they are hoping to push the idea of functional qualification out to a wider audience. They ought to be able to leverage the marketing and sales teams of SpringSoft to do that. They will also benefit from a larger pool of apps engineers who, with some training, will be able to support more customers as they ramp up on Certitude, Certess’ main product.
The next two announcements I’m aware of are from Cadence.
First, they are open-sourcing the e and SystemC-language versions of the OVM (now available for download on OVM World). I was really excited to hear this news in a pre-brief on Friday, but the excitement wore off a little when I realized the OVM-e code was pretty much the same as what was released in the November 2008 version of IUS. Basically, on the e side the eRM is being superseded by the OVM to make it easier to align multi-language testbenches. The primary enhancements you get by using the OVM-e code instead of the eRM are:
- Use of namespaces over class name prefixes
- Base types such as ovm_agent, ovm_monitor, and ovm_bfm have been added
- A standard configuration struct base class is now part of the library
- Test phases (similar to what’s in the VMM) are now available at runtime
- hard reset
- init link
- Improvements added to allow constraining of sub-sequences from a higher level sequence
- e sequences are now more closely aligned with SystemVerilog OVM sequences
- More control over the “do” process (pre-do, post-do, etc)
- TLM between sequencer and driver
- More flexibility so you don’t have to call the solver when randomization is not needed
Second, Cadence announced a new licensing model for verification IP. Users can purchase a batch of licenses, any one of which can be used for any of the verification IP components in the Cadence portfolio. That should make planning easier for companies who need to purchase a large number of different types of verification IP licenses (full disclosure: Verilab has developed its own verification IP for the OCP protocol).
After Cadence comes an announcement from Synopsys about the release of the VMM Low Power book. A PDF version of the book is available to Synopsys customers on Solvenet. Synopsys will be presenting a tutorial on the VMM-LP tomorrow, February 24, at DVCon.
Finally, there was an announcement by Jasper:
To be honest, I don’t really understand what Jasper is trying to introduce here. There are quite a lot of buzzwords in this press release… I’m scheduled to speak with Kathryn Kranen, CEO of Jasper, on Wednesday to get more info.
So that’s it! If I’ve missed something please let me know.