Cool Verification

Yesterday afternoon I arrived in Japan in preparation for the Verification Now seminar coming up tomorrow (Monday, October 27) in Yokohama. 

Last Tuesday I was in Santa Clara presenting the first of the 2008 Verification Now seminars (the next one is tomorrow, October 21, in Austin).  About 50 attendees showed up to hear presentations on Requirements Based Verification, Layered Stimulus Generation in the VMM and OVM, and to see demonstrations from Certess, Denali, and SpringSoft. 

The trip was a bit of a marathon – I flew out to Santa Clara Monday afternoon, arrived at 5pm, and then headed over to the Denali office to work on recording a portion of the material in webinar format to assist with the translation efforts for the seminar in Japan.  Apparently we’re going to have a translator in Japan live-translating my presentation.  Participants will be able to wear headphones and listen to the translator if they don’t like listening to me directly, UN style!  I was at the Denali office until around 8:30pm or so, and then headed back to the hotel to get some rest.  Unfortunately, some pre-seminar jitters kept me awake later than I’d hoped (worrying that I wouldn’t hear the alarm and would be late to my own seminar ;-). 

Tuesday we'll be kicking off the Verification Now "world tour" in Santa Clara.  As I mentioned a few weeks back the seminar consists of two topics.   

Tomorrow (Thursday, October 2) the SystemVerilog User's Group (SVUG) is holding an event in Austin from 2pm to 7pm at Cool River Cafe.  My colleague Jason Sprott, Verilab's VP of Consulting, is presenting, as are Cliff Cummings and others.  Jason, Cliff, and I will all be on a "Stump the Experts" panel moderated by Kelly Larson from MediaTek.  The panel is from 5:20-6pm.  Unfortunately, I'm going to miss the earlier portions of the event due to other commitments but I hope to see those of you who stick around for the panel and the subsequent cocktails and hors d'oeuvres.