SystemVerilog Interoperability for Heavy Hitters!
June 09, 2008
Day one at DAC is half way over. The general perception I've gotten from many of the vendors is that things seem slow. Many didn't realize that it is cheap/free to get in the exhibition hall all week and were surprised at the turnout as they thought it was "free Monday." Turnout was light at my presentation this morning as well, though perhaps "light" isn't the right word for it. I ended up giving my talk about SystemVerilog Interoperability to Janick Bergeron (Synopsys, author of the VMM book), Cliff Cummings (Sunburst Design, SystemVerilog trainer and member of the SV and Verilog standard committees), Allan Crone (Mentor Graphics OVM guru), and Mark Glasser (Mentor Graphics OVM guru). All I needed was to have someone like Mike Stellfox or Stan Krolikoski from Cadence join us and we could have had our own panel discussion on VMM vs. Cadence OVM vs. Mentor OVM! To say I was nervous would be a bit of an understatement :-).
Overall, I think the talk went well. There was some good discussion between the attendees regarding the developments simulator vendors are making on the SV language interoperability front. There was also general agreement from the attendees (except Cliff) that SVTB is difficult for designers to learn properly, as it can be complicated to use correctly if you're not familiar with OOP software design practices.
One bit of feedback I got was that it would have been useful to show the audience what the near-term future holds in terms of improved interoperability between the vendors. I agree that things should start to improve given the fact that the VMM and OVM are open source and are available to the major simulator vendors. However, it remains to be seen how quickly the necessary features will be incorporated into the various tools in order to allow true interoperability of SV source code. An additional point of contention that came up was my assertion of the fact that SV is not interoperable is anything other than vendors misinterpreting vague sections of the SV spec. The point I was trying to make was that vendors chose to implement specific SV features and leave out others which is nothing to do with a vague specification at all! For example, the Synopsys version of SystemVerilog is based heavily on Vera, while the Mentor implementation is not. Similarly, Mentor and Cadence implemented features of the language that suited their respective expertises and ideologies. While that may be politically beneficial to the EDA vendors it is certainly not beneficial to end users.
If anyone who couldn't make it is interested in seeing the presentation, let me know and perhaps we can arrange another showing (either at DAC or at some point in the future). Also, any of the attendees should feel free to add their comments (good or bad) below.