Update: June 18, 2008: Added links to additional commentary about the merger at the bottom of this post.
Update 2, June 18, 2008: What is Certe? Clarified language and made reference to comments of this post for more discussion.
Last Thursday, after DAC had pretty much come to a close, my colleagues and I headed over to the California Adventure theme park for a bit of fun. One of the highlights was the Tower of Terror, based on the old TV series, The Twilight Zone. "The Twilight Zone" always opened with the following intro from Rod Serling:
"You unlock this door with the key of imagination. Beyond it is another dimension. A dimension of sound. A dimension of sight. A dimension of mind. You're moving into a land of both shadow and substance, of things and ideas. You've just crossed over into...The Twilight Zone."
I felt like I'd entered into "The Twilight Zone" this morning when I opened my email to see mail from current and former colleagues sharing the announcement that Cadence has offered to purchase Mentor Graphics for $16 per share. The impact such a purchase could have on the EDA industry are enormous and span many technical and business areas. As it turns out, I'm only really qualified to comment on one - verification, so the rest of this post will be focused on that topic. How would a merger affect the lives of those of us who do hardware verification for a living?
As it turns out, Cadence and Mentor already got a head start on just such a merger back in August when they announced they were working together on a unified verification methodology, the OVM. Though they've been working together for almost a year now on the library, they've still got a ways to go before I would say they've truly come to an agreement on what a testbench should look like. As I discussed in a presentation I gave at DAC last week, there are really two versions of the OVM - the Mentor TLM-style approach and the Cadence eRM-style approach. With the release of OVM 2.0 sometime in August some of these issues should be resolved, but there are still deep philosophical differences between the Mentor and Cadence technologists in the verification space.
If a merger were to occur, one of the benefits from a financial perspective would seem to be that you wouldn't need quite so many people thinking deep thoughts about verification methodologies (read, massive layoff). If you look at what happened at Cadence when Verisity was acquired, you'll see that the old-guard from Verisity ended up running the verification show. In fact, I won't name any names but some of the original folks from Cadence who several years ago tried to convince me that I was an "e bigot" and could do everything I wanted in SystemC are now singing a much different tune. Mentor definitely has some very experienced and well respected folks working in their verification division who are very passionate about their approach. I believe the Mentor folks would continue to contribute in a positive way but would end up towing the Cadence line in certain areas such as the value of field macros or the benefits of the OVM factory that really come out of the whole Aspect Oriented approach to verification.
Besides more general agreement on verification methodology issues, what else could change? Well, there's the whole debate about the future of the e language. Effectively you'd have Cadence vs. Synopsys; one with e support and one without (for now). I'm not sure, but I think in a one on one match-up there may be more interest in starting new projects with Specman. Only time will tell though.
On the simulator side, Cadence would benefit immensely from integrating the SystemVerilog language support found in Questa into Incisive. Cadence seems to have the weakest support for the SystemVerilog standard at the moment so such a move would certainly be welcome by current Cadence customers. I could see Cadence maintaining support for both IUS and Questa, even in the long term, due to the fact that many FPGA developers use Questa in a Windows environment, something that is simply not possible with recent versions of Incisive (AFAIK). I've personally found Questa to be extremely convenient to use due to the fact that I can run it easily on my Windows-based laptop along with Certe, Mentor's SystemVerilog
IDE development environment (currently in beta, see comments section for a discussion of why this tool might not be as "integrated" as would be expected from a full IDE). Cadence also doesn't seem to have an answer to Mentor's inFact Intelligent Testbench Automation tool, though I'm not sure how widely inFact has been used in real designs.
All in all, if I was working in the verification division at Cadence I'd probably be pretty pleased with today's announcement. If I was working at Mentor I think I'd be worried. Getting absorbed by the Borg of the EDA industry probably isn't what most of the folks at Mentor had in mind. As a user, I'm not sure what to think. I like the idea that my beloved e language could get a boost, but am unnerved by the possibility of even less competition in the EDA industry (which is never a good thing). Of course, Synopsys would still be around and kicking - perhaps reducing the industry down to two major players has the potential to drive even more innovation as these two juggernauts go head to head.
For more info, check out:
- Analysis of the merger over at Chip Design Magazine
- Chris Edwards: Mentor's Big Decision
- Gabe Moretti: Cadence's Arrogance
- Sramana Mitra: Cadence Takes a Page Out of Microsoft's PlayBook
As always, thoughts, comments, and questions appreciated! And now, back to your regularly scheduled programming... (At least in my house, I've got a two year old!)