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June 2008

1647-2008 e Language Standard Updates and Gary Smith is NOT Smarter Than a 5th Grader

This just in from Andy Piziali, Chairman of the IEEE 1647 e Language Working Group - IEEE 1647-2008 has just been released!  New features include (from the press release):

  • Method ports for easy exchange complex data structures and control between verification components and designs under verification  
  • Sequences that define, generate and apply complex stimuli that are specifically tailored for module-to-system reuse  
  • A host of other features that enable scalability and module-to-system reuse by simplifying module naming hierarchies, structuring data and increasing performance  

Richard Goering had an interesting writeup over at SCDsource on the announcement but made the mistake of quoting Gary Smith:

Gary Smith, chief analyst at Gary Smith EDA, said that SystemVerilog and "e" are not natural competitors. The "e" language, he said, is typically used in large system designs, while SystemVerilog is an RTL language that replaces Verilog. What "e" language backers need to watch, he said, is SystemC – but SystemC's test class library is still "fairly immature."

Huh?  I'm sorry, but the SystemC SCV library, IMHO, competes (poorly) with SystemVerilog.  I don't know of many companies using SystemC for verification.  Of the two I'm thinking of, one of them didn't even know that there was such a thing as SCV until I mentioned it to them recently.  In fact, I'd be interested to hear if any readers of this blog actually use SCV or better yet, even use SystemC for real constrained random verification work (not modeling - I know it's popular in that area).  Gary has fallen victim to the fallacy that SystemVerilog is a single language when, in reality, it is three (design, testbench, and assertions).  The e language competes (rather well thank you very much) with the "Testbench" portion of SystemVerilog.  Based on the above comment I'd say Gary is not smarter than a 5th grader!

As always, questions and comments welcome.

Synopsys Open Sources the VMM

Newsflash - I just got a note from Karen Bartleson at Synopsys letting me know that the VMM is now available for download under an Apache 2.0 open source license!  This is good news - for months the debate between OVM and VMM has been centered around the licensing terms required for each.  Now we can focus on the actual technical differences between the libraries.  I'm also hoping that it won't be long before we see new simulator versions from Cadence, Mentor, and Synopsys that can read both libraries (given the interest each vendor will have in stealing away customers from one another).  This should certainly add some spice to the work of the Accellera VIP TSC!

Also, on another interesting note, I just noticed today that Janick Bergeron of VMM fame has now started his very own blog, Verification Martial Arts.  Welcome to the blogosphere, Janick!  Now we just need to get some folks from Mentor and Cadence blogging and we can have all sorts of fun :-).

Update - Birds of a Feather

Time is progressing and unfortunately I haven't done as much as I'd like to organize the Birds of a Feather session I proposed a couple of months ago.  Why not?  Some of you may have noticed my blog went into a bit of a hiatus during the March and April time frame.  Why?  Well, the reason was related to issues surrounding the relationship between Cool Verification and my employer, Verilab.  What were these issues, you may ask?  My boss, Tommy Kelly (Verilab's CEO) has done a good job of summarizing the ins and outs of Corporate Blogging and the issues he and I faced on his new blog, Darkling Wood.  Topics include:

  • possible brand dilution
  • IP ownership
  • appropriateness of content

The end results of our discussions were that I'm back to blogging again and Tommy himself has taken the blogging plunge!  Perfect timing, as it provides yet another topic of interest for the DAC 2008 Birds of a Feather session on blogging.  Now, as I mentioned I've done a crappy job promoting this, but here is the general idea.  Send me your name letting me know you're going to attend.  Show up somewhere in the neighborhood of rooms 201B and 201C at the Anaheim convention center on Wednesday, June 11 around 6pm.  I'll be there and so will at least 3-4 others who have confirmed with me.  If 10 confirm by the Wednesday afternoon of DAC we'll actually have a room.  If less, we'll go grab a beer and have some ad hoc discussions. 

Who should attend?  Bloggers, people interested in starting to blog, marketing directors looking for info on how best to communicate with bloggers (hint, don't send me a form mail, personalize!), CEOs wondering how to get their employees to start blogging, and anyone else curious about the impact blogging is already starting to have on the EDA industry.

So, send me a note if your planning on attending.  Also, feel free to catch up with me any time at DAC itself - I'll be presenting at the Real Intent booth on Monday, June 9 (more details to come soon) and may also be seen hanging out around the Novas booth with my colleague David Robinson who will be speaking on the topic of Verification Planning Monday through Wednesday.

On SystemVerilog VIP Interoperability

As I mentioned last week, Verilab is now a member of Accellera.  I've been involved with the newly formed Verification IP Technical Standards Committee.  One of the first objectives of the committee will be to create a Design Objectives Document, otherwise known as a DOD.  Some possible objectives of the committee were presented yesterday during the weekly TSC conference call which spawned an email thread between some of the participants (including myself).  The issue being - what is the scope of the committee?  Is it to come up with a common methodology to be used by all vendors?  Is it to create an API to be used to allow communication between competing methodologies?  Or, is the purpose of the committee more basic than that? 

Continue reading "On SystemVerilog VIP Interoperability" »

The Power of "New Media"

At DVCon this past February I had the pleasure of meeting Ron Ploof, New Media Evangelist for Synopsys.  Ron helps run (among other things) the Synopsys blogging site.  He also has his own blog, RonAmok!  Earlier today Ron posted a video describing his experiences after posting a video about his bad experience with buying flowers online (got that?).  It's a fascinating look at what happens when your average, everyday Joe (or Ron in this case) posts content about a company on the Internet.  Though I've never posted video, I have seen this sort of thing happen on Cool Verification.  I'd highly recommend folks take a look (and special kudos to Ron - I'm impressed with the quality of the video!).

DAC, Accellera and Web 2.0

It's been awhile but don't worry, I'm still here!  If you'd like to see what I'm up to in real-time feel free to check out my Twitter feed (also from the Cool Verification homepage).  I'm testing out Twitter (and some other new web apps such as Jott and Remember the Milk) in preparation for DAC and apparently as a way to convince myself and my wife (ok, just my wife) that I need an iPhone.  I've also got some cool things to announce about Verilab and our activities at DAC this year - look for more in the next week or so on that front.  Also, if you look at the Accellera membership roster you'll notice a new name has appeared - that's right, Verilab is now a member!  I called into my first Accellera meeting last week - the Verification IP Technical Subcommittee meeting.  No major drama... yet :-).

Stay tuned...