Cool Verification

This just in from Andy Piziali, Chairman of the IEEE 1647 e Language Working Group - IEEE 1647-2008 has just been released!  New features include (from the press release):

• Method ports for easy exchange complex data structures and control between verification components and designs under verification  
• Sequences that define, generate and apply complex stimuli that are specifically tailored for module-to-system reuse  
• A host of other features that enable scalability and module-to-system reuse by simplifying module naming hierarchies, structuring data and increasing performance  

Richard Goering had an interesting writeup over at SCDsource on the announcement but made the mistake of quoting Gary Smith:

Gary Smith, chief analyst at Gary Smith EDA, said that SystemVerilog and "e" are not natural competitors. The "e" language, he said, is typically used in large system designs, while SystemVerilog is an RTL language that replaces Verilog. What "e" language backers need to watch, he said, is SystemC – but SystemC's test class library is still "fairly immature."

Huh?  I'm sorry, but the SystemC SCV library, IMHO, competes (poorly) with SystemVerilog.  I don't know of many companies using SystemC for verification.  Of the two I'm thinking of, one of them didn't even know that there was such a thing as SCV until I mentioned it to them recently.  In fact, I'd be interested to hear if any readers of this blog actually use SCV or better yet, even use SystemC for real constrained random verification work (not modeling - I know it's popular in that area).  Gary has fallen victim to the fallacy that SystemVerilog is a single language when, in reality, it is three (design, testbench, and assertions).  The e language competes (rather well thank you very much) with the "Testbench" portion of SystemVerilog.  Based on the above comment I'd say Gary is not smarter than a 5th grader!

As always, questions and comments welcome.