My first stop of the day was to sit in on session 4.2 - High Level Validation Models. A few things caught my attention at this session. First, and reminiscent of my experience last year at DATE was a comment made by the third presenter, Joao Marques-Silva from Southampton University in the UK. The title of Joao's presentation was "Algorithms for Maximum Satisfiability Using Unsatisfiable Cores." During his opening remarks, Joao mentioned that knowledge of SAT solvers was required to understand his presentation. He continued: "If you don't understand SAT, tough!" Eh? Many of the talks last year had this type of strong academic bent. I believe many of the session attendees did understand SAT, but for those of us who didn't the discussion that followed was absolutely meaningless.
In addition to the somewhat academic focus, a major issue with DATE is that the program is so massive (seven sessions going on simultaneously today - each with 3-4 papers, plus fringe meetings, plus tutorials, plus panels in the exhibition hall) that it is difficult to find the one or two things in each time slot that you might actually find useful. I missed the Accellera Open Industry Meeting this afternoon and a Doulos tutorial Tuesday afternoon on TLM 2 simply because I hadn't known where to look to find the times for these events.
One of the best things about today was I got to add to my collection of photos of industry luminaries. Though I wasn't able to get the lighting just right in Lightroom this evening, the photo below shows Ted Vucurevich, CTO of Cadence (left) and Mac McNamera, VP and General Manager at Cadence (right). Mac's claim to fame in my book is that he is the author of the famous Verilog mode for Emacs. His other claim to fame can now be that his picture has appeared on Cool Verification! ;-).
Later on this morning, I had a chance to speak with Fabian Delguste, Senior Manager, Corporate Applications Engineer (below left) and Maria Christina Borelli, Product Solutions Sales Manager, Europe (below right) about the recently announced Eclypse Low Power Solution from Synopsys. Within the Eclypse platform it is currently possible to model low power states using UPF files along with a combination of VCS and MVSIM. VCS will natively support additional power modeling capabilities in the near future including the ability to annotate a verification plan with low power coverage information.
Over lunch, I had an excellent discussion about the OVM and some of interesting features of Questa with Allan Crone and Joseph Derner of Mentor Graphics. Allan helped me through the TLM concepts encapsulated within the OVM and demonstrated some of the SystemVerilog debug features (including an ability to read transaction info from OVM-based code for display in the Questa waveform viewer). I'll have more to say on the topic of the OVM in the coming weeks and months as I continue to ramp up on the topic.
After chatting with Mentor I headed up to the press room to relax for a bit and go through my notes and photos from the day. The press room at DATE has (at least for the last two years I've attended) been run by Monique Wittmann (below left) and Freddie Santamaria (below right). I'd like to thank them for being such good sports when I asked if I could snap a few photos!
My final major stop for the day was at the Forte Design Systems. I've always wondered what exactly Forte did and, after bumping into Brett Cline at the Troublemakers Panel at DVCon a few weeks ago, I decided to bite the bullet and swing by the booth to hear their pitch. I spoke with Applications Engineering manager Reed Taylor who gave me a comprehensive overview of Forte's Cynthesizer tool. Cynthesizer allows users to write primarily untimed C++ models with some SystemC (to model pin level timing) and to synthesize the resulting code to RTL. As it turns out, Cynthesizer works well with Calypto's Sequential Logical Equivalency Tool (SLEC). SLEC can formally prove that untimed C++ code such as that used with Cynthesizer is equivalent to generated RTL. Sounds good, right? The thing I didn't like after my discussion with Reed was the fact that testbenches for this sort of C++ based design are also meant to be written in C++ and/or SystemC. I've built testbenches in SystemC in the past and found it difficult to fully utilize constrained random approaches and generate associated coverage. According to Reed, Jeda may have some technologies to help address my concerns, but I wasn't able to track anyone down from the company at the conference today.
Before calling it quits for the day I wandered around with my camera and came up with a couple of interesting shots. The photo below shows Cornelia Grabbe, Senior Design Engineer at TRS-STAR GmbH demonstrating a robot made (I believe) out of some programmable FPGAs. The robot apparently had nothing to do with the company's sales pitch at the booth but was designed instead to catch people's attention.
A bit later I came across some of the many women working the coat checking facilities at the conference center. It took a few minutes but I eventually realized they didn't speak much English. I think they initially thought I was taking photos for some sort of important news organization (apparently they hadn't read about Ed Sperling's roundtable discussion at DVCon). I think I was able to explain that these pictures were just for the web (i.e. my blog), but thinking back I'm not sure I would believe it if someone speaking in a language I didn't understand came up to me and asked for my photo...!
That's it for today. I'm not entirely certain I'll be spending much time at DATE tomorrow or not as I've got some other commitments. Anyone out there attend any interesting sessions or learn anything new at DATE this year? Anything I should track down tomorrow in the Exhibition Hall? Drop me a line and let me know!