A Busy Day at DVCon
DVCon 2008 Best Paper Award

The Brewing Standards War - Verification Methodology

Back in August when the OVM was announced one of the big unknowns was how Synopsys was going to respond.  If Karen Bartleson's recent post on standardizing verification methodologies is any indication, the response is going to be to attempt to slow down and gain some element of control of the OVM via a drawn out battle in an Accellera standards committee. 

To be perfectly frank, once VCS supports enough of the SystemVerilog standard to run the OVM (and I can't believe they'd be stupid enough not to be working on such capabilities) this whole discussion is a moot point.  Synopsys had a chance a few years back to release the VMM and maintain some sort of technical leadership in the area of verification methodologies.  Sadly, they chose instead to keep their library to themselves, sowing seeds of doubt in VCS users who might have adopted the VMM if not for the worry that it would be difficult, if not impossible to run it on competing simulators.  In addition, they've let things slide a bit recently to the point where the VMM library simply doesn't have the same robust capabilities as the OVM. 

For example, the base VMM library doesn't scale well from module level to full chip test environments, due to the restrictive nature of the vmm_env top level object.  They also tend to require (again, due to the way envs are constructed) a very flat hierarchy of objects in the testbench, making it inconvenient to encapsulate things in a way that makes it possible to reuse large collections of objects.

Another area where the VMM is lacking is in its inability to easily support the "virtual sequence" concept supported by the OVM.  On a recent VMM-based project I had to implement my own virtual sequence infrastructure to deal with test scenarios that needed to procedurally access several drivers within the environment.  Why should I have to spend time coding something this basic?  The concept has been around since the early days of the eRM back in 2002.

Basically, over time, Synopsys has grown complacent with their perceived leadership in the area of SystemVerilog methodology libraries, and now finds themselves in the unusual position of having to play catchup to the Mentor/Cadence coalition.  I understand that business is business, but if Synopsys is serious about being involved in a verification methodology standards effort they should start by releasing a version of VCS that supports the constructs required to run the OVM and release the source of the VMM so that other simulation vendors can incorporate any necessary changes into their platforms.  That way the industry can openly evaluate the merits of both technologies and have an honest, user driven technical discussion about the pros and cons of various approaches to testbench design without the typical marketing BS.