The Expo Reception Needs Change Bars!
The Brewing Standards War - Verification Methodology

A Busy Day at DVCon

Updated 2/21: Cleaned up photo formatting.

Phew.  It's been a busy day!   Since I'm nodding off as I'm writing this, I thought I'd give a brief summary of what I was up to today and highlight some of the photos I've taken.  Hopefully tomorrow morning I'll have a chance to write things up in a bit more detail.


The general conference kicked off this morning with an opening session given by Stephen Bailey and Tom Fitzpatrick from Mentor Graphics.  Next up for me was Session 2 - Applications of the System Verilog Direct Programming Interface put on by "Team Stu".  I really enjoyed the session, as it showed a couple of real applications of the DPI, as well as some work done by Mentor Graphics that will allow Questa users (as of version 6.5) to directly access C++ objects from SystemVerilog and vice versa.


I was then going to attend Session 4 on SystemC in verification but was suckered into checking out Session 3 - Assertion-Based Verification of Low-Power Designs instead.  Oops!  The middle presentation given by Bill Winkeler describing how to use the Cadence toolset to determine whether you've tested all possible low power combinations was good.  The others were pretty poor.  The main problem I had with the whole session was that the content was entirely vendor generated.  Perhaps in the future there should be a cap on the number of papers from Mentor/Cadence/Synopsys so that there is more room for user generated content.  Basically, out of the 6 presentation I saw today only two were from someone other than one of the big three EDA companies.


I had a fascinating meeting over lunch (one of a couple corporate blogging related discussions I have scheduled for this week), and then it was off to see Wally Rhines' keynote address on "Ending Endless Verification".  The keynote was interesting.  I was hoping to find a summary to link to from one of the professional journalists covering the event, but haven't seen any yet, so I'll summarize as follows:

  1. We need a 100x improvement in verification productivity.
  2. Intelligent Testbenches, formal methods, and transaction level modeling (TLM) may together be the technologies to bring about the 100x improvement.
  3. (left unsaid) Mentor has technology in all of these areas.


After the keynote John Cooley (sporting a gnarly beard) took the stage for his infamous Troublemakers Panel.  Again, I'm sure the event will be covered by the professionals. When I find the links I'll pass them along.  I felt Cooley was a bit more civil than last year, but as usual he showed a true lack of understanding of anything verification related. Frankly, I could care less when he discussed the ins and outs of the back end tools with Mentor, Synopsys, and Magma.  This is a conference on Design and Verification.  Nothing in the rest of the conference has anything to do with Blast, Talus, or any of the other tools that the panel spent at least a quarter or more of the time discussing. 

After the Troublemakers Panel I had the pleasure of speaking with Mitch Dale from Calypto.  Because I'm about to fall asleep I'm going to do the lazy thing for now and provide a link to an article by Mike Santarini written in 2005 about the company.  Basically, Calypto provides tools to do what they call Sequential Logical Equivalency Checking (SLEC).  To make a long story short, they can prove equivalence between C/C++ models of a device and corresponding RTL, or even equivalence between two versions of an RTL module where one has been tweaked (for example, to lower power consumption) but where you'd like to show that no functional change has occurred.  It seems like a great idea, and I was left wondering if any readers of this blog have used the tool and would care to comment on its usefulness.