Not surprisingly, I've yet to hear anything from Synopsys regarding the recent rumor about VCS supporting the e language. While waiting to learn more, I thought I'd take a guess as to what sort of support might exist.
Believing that Synopsys would actually openly support 'e' ranks up there with believing in the Tooth Fairy (more disturbingly) and Santa Claus. A more realistic possibility could be for Synopsys to release a tool to convert 'e' to SystemVerilog. That would let them sell into companies with a large base of existing 'e' code, but still focus support on SystemVerilog. If you look back in time a couple of years, you'll see that Synopsys has been offering an 'e' migration service to help clients port 'e' to SystemVerilog. It's not such a stretch of the imagination to suppose that they've been able to neatly package up lessons learned over the years into an automated tool to assist with some of the heavy lifting. Add in some native VCS support for constructs that are not easy to duplicate with straight SystemVerilog and you'd have a nice marketing bullet to help convince the heads of purchasing departments at large companies to completely make the switch.
As always, comments welcome!