One of my main goals during my trip to CDNLive! in San Jose a couple of weeks ago was to find out more about the Mentor/Cadence OVM SystemVerilog library. I spoke with several folks from Cadence, and also pinged someone from Mentor Graphics who was attending the EDA Tech Forum over in Santa Clara. The big question in my mind has been trying to understand how the AVM and URM were going to be merged together into a common library that would remain compatible with legacy environments.
The answer, it turns out, is that the URM is mostly a superset of the AVM. The URM deals with system level methodology issues that are largely not addressed by AVM, and both libraries use transaction level modeling (TLM) concepts in some way, shape, or form. Cadence and Mentor engineers were able to work together to merge the two libraries by leaving the URM largely intact and adding a couple of extra runtime phases - "elaborate" and "end of elaborate" - in between the existing "post new" and "pre run" phases.
Cadence claims the resulting OVM library will be 99% compatible with AVM v3.0 and URM 6.2. As far as I'm concerned, the fact that Mentor and Cadence are working together on this is massively good news. Getting two of the three major EDA vendors on the same page methodology-wise will help speed up adoption of SystemVerilog and should make it easier for third party companies to produce verification IP. Additionally, it's exciting to hear that we'll start to see more influence from the e Reuse Methodology on SV testbenches. As I've mentioned in the past, the eRM is the most comprehensive methodology out there, but its adoption has been hampered by the politics surrounding the e language.
The OVM library is still under joint development by Mentor and Cadence engineers. My understanding is that the library should see the light of day in the form of either a public website or private customer betas sometime within the next couple of months. As I learn more I'll be sure to keep everyone posted.