For several years I somehow managed not to attend any conferences. Today, I'm getting ready to fly to San Jose (with a quick jump up to Seattle for the weekend) for conference number four - CDNLive!. The conference program looks interesting, and I'll get to staff part of the Cadence IPCM Partner booth on Tuesday evening. If it wasn't already obvious from the name of the conference, this required question from the online registration form pretty much sums up what I expect to learn this week:
Which company do you believe is best at delivering inventive solutions that enable you to achieve breakthrough results?
Uh... Cadence? :-). I hope to have the opportunity to meet those of you who plan to attend. As I mentioned earlier, I'll be at the Cadence IPCM Qualified Partners booth on Tuesday evening to answer questions about Verilab and to give away ~4-5 copies of David Robinson's excellent new book, Aspect Oriented Programming with the e Verification Language. Luckily for me, the book is travel friendly and I was able to fit a stack in my carry on luggage.
By the way, in case your curious, here are the sessions I'm tentatively planning on attending:
Monday, 10th September
- 10:50–11:35: Roadmap 1.1
- 11:40–12:25: Technical Panel 1.2
- 13:45–14:30: Session 1.3 – HW and Embedded SW Verification Flow Based on Incisive Software Extensions and the Xtreme System
- 14:35–15:20: Session 8.4 – How to Overcome Challenges in Designing a DDR2/DDR3 Memory System
- 15:35–16:20: Session 2.5 – Scalable RTL in Design and Verification
- 16:25–17:15: Session 1.6 – Design of a Reusable, Layered Traffic Generator for Verifying Multi-Layered Communication Devices
Tuesday, 11th September
- 10:25–11:10: Session 1.7 – Simplifying Vertical Reuse with Specman Elite
- 11:15–12:00: Session 1.8 – Translation of an Existing VMM-Based SystemVerilog Testbench to URM
- 13:50–14:35: Session 6.9 – Modeling Semi-Ideal External Components Co-Simulation
- 14:40–15:25: Session 3.10 – Automating Functional ECOs using Encounter Conformal Technology
- 15:40–16:25: Session 1.11 – Speeding up HW/SW Co-Development using HW Emulation
- 16:30–17:15: Session 2.12 – Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
Wednesday, 12th September
- 9:00–9:45: Session 2.13 – Integrating Design IP and Verification IP to Ensure Quality and Enhance Productivity
- 9:50–10:25: Session 8.14 – How to use SPB 15.7 to Simplify Your DDR Constraints
- 10:30–11:15: Session 2.15 – Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
- 13:00–17:00: Incisive ESL verification solution featuring SystemC, hardware acceleration/emulation (2 hrs) and Advanced verification featuring the Incisive Plan-to-Closure Methodology w/SystemVerilog (2 hrs)
Anyways, my flight to Seattle is now boarding... Stay tuned throughout the week for my CDNLive! trip report.