How Engineers and Managers Communicate: An EDA Consortium Video
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SystemVerilog and Specman/e - Why Can't We All Just Get Along?

Recently, I took a look at Cooley's verification survey and came to the conclusion that his methods were flawed. I had the opportunity to speak with Cooley at the Denali Night Fever party this past Tuesday regarding the accuracy of his survey.  It was a challenging discussion, what with a band playing 20 feet away and Cooley sporting a pair of foam earplugs, but it was clear that Cooley still has faith in the results of his survey.  Why?  He's checked with some friends who work as actuaries and also has sanity checked his data against other surveys done by folks such as Gary Smith.  By the time we finished our chat, I wondered if maybe I'd been too harsh on Cooley. 

On Wednesday afternoon, I attended a get together of the Cadence Verification Alliance partners (Note: Verilab also partners with Mentor Graphics and Synopsys).  The presenters, including Mike Stellfox and Joe Hupcey, among others, were very upbeat about the future of Specman and the recent success they've had winning new business.  I asked them about Cooley's survey, and how it could be true that people are switching to SystemVerilog in droves and at the same time Specman continues to do well in the market.  There were a couple of interesting points in their response:

  1. The end users who respond to Cooley's survey don't make business decisions.
  2. There doesn't need to be an either-or choice.  Why not use both e and SystemVerilog?

I'd like to specifically touch on the first point.  I've finally come to the realization that decisions about whether to use SV, e, SystemC, C, or some other language come down to business decisions at the end of the day.  Somewhere, the CEO, VP, or engineering director is going to look at the amount of money they have to spend on tools and what kind of a deal they can get from the EDA vendors.  Verification tools are only part of the package.  So, if a company decides that Cadence is offering the best overall deal on an entire suite of tools, they'll end up choosing 'e' as their verification language of choice, at least until Cadence's support of SV improves to the same level as their 'e' support.  If the best deal comes from Mentor or Synopsys, they'll go with SV. Or, perhaps they're going to use NEC as their foundary and subsequently decide to use CyberWorkBench, an entirely C-based design and verification flow (worth a look if you don't mind the lack of constrained random or functional coverage support).

To many of you the Cadence response may seem like the standard marketing response you'd expect from any of the large EDA companies when unfavorable news is reported regarding their products.  And I would wholeheartedly agree with that observation, except for the fact that they are backing up their words with a strong product roadmap based on Specman and the URM.  For example, a new generation engine has been developed to remove significant limitations that existed in the old generator.  On top of that, significant enhancements have been made to the graphical constraint debugger.  Then there is the new Incisive Software Extensions (ISX) package which allows users to instantiate embedded software in their testbench as if it was another part of their HDL DUT.  Basically, this allows you create constrained-random tests and use functional coverage to verify embedded software.  Additional product enhancements were also covered during the session.  I'm not sure which others I can share publicly, but I left the meeting feeling confident that a recommendation to use Cadence verification tools would not lead someone down a dead-end path anytime soon. 

SystemVerilog is winning the hearts and minds of the readers of Deepchip.  Cadence is putting a lot of effort into improving their verification flow, including enhancements to both Specman/e and SystemVerilog.    What does that mean to you in the end?  First, if you're an 'e' user, and don't have a business reason to switch to Synopsys or Mentor Graphics, there is really no reason to migrate existing testbench infrastructure to SystemVerilog, or to worry about putting effort into new 'e' development.  If you're a Mentor or Synopsys customer, SystemVerilog is your only option so the choice is easy there, but you'll still have to decide whether you want to go with the AVM or VMM approaches.  The VMM and AVM serve similar purposes, but selection of one or the other will lock you into using Mentor (AVM) or Synopsys (VMM) for now, at least until support for the SystemVerilog standard improves between the vendors.  (Note - in the case of the Synopsys VMM you'll have to also wait until the library source is released under more favorable licensing terms).

Still confused?  Wait a few years and we'll likely have a clearer picture of where things are headed.  In the meantime, remember that we're getting to the stage where not making a choice at all (i.e. not moving to either SystemVerilog or Specman) is going to put you and your team at a competitive disadvantage when it comes to bringing well-verified products to market.