When I went to DVCon back in February I had the best of intentions. I queried everyone at Verilab to come up with a list of intelligent questions that I could ask the various presenters. Then, while I was there I realized that it was difficult enough to capture what was happening, let alone to track down someone who would know the answer. The chance to ask these questions has passed, but in an attempt to inspire myself for the week ahead, I thought I'd share with everyone the questions I was hoping to answer at DVCon:
- Why does each EDA company think its tool flow is so much better than all the rest?
- Why is there such a focus on coverage these days as opposed to stimulus and response checking? Do the major players in EDA feel these problems have been addressed and that coverage is the last difficult problem to tackle in this area?
- What's going on with the SPIRIT consortium?
- What is the interest level in SystemVerilog for testbench development.
- Has there been any progress in coming up with transaction level modeling standards to allow interoperability between SystemC models from various vendors, particularly cycle-based vs. event-based models?
- When will System Verilog Assertions be truly integrated with 'e'? What will happen to the 'e' temporal language?
- Will Cadence provide SystemVerilog libraries to support things like sequences? How will these be implemented given the lack of AOP/when inheritance in SystemVerilog?
I don't have the DATE program available as I'm writing this post, so I'm not sure whether there specific sessions that would help me answer some of the above questions. I do believe there is some activity related to the SPIRIT consortium. I'll need to confirm that when I have an Internet connection (and when I've had some sleep).