All I wanted to do this morning was get a permutation of an array in my SystemVerilog testbench. Was that too much to ask? Sure, I could do it procedurally but that's no fun. I was hoping SystemVerilog would have some convenient features to allow me to shuffle the list without extra code. After browsing through the LRM, the SVTB VCS manual, and the Doulos SystemVerilog GRG, I finally noticed that there was a handy array member function called "shuffle()" that returned a permutation of the current list. Imagine my disappointment when I realized a few minutes later that VCS doesn't yet support shuffle, at least in the version I'm using.
I've been building up a list of questions related to my recent SystemVerilog experience. When I have a few spare minutes I'll try to capture some of those here. Do any of you have recent experience with SVTB you'd like to share? I've heard a lot of talk from vendors about all of the delicious buttery goodness that is SystemVerilog, but when I've actually talked with real life users of all of the major EDA vendors they are inevitably still running across tool issues, unsupported features, etc.