Thursday morning I attended a panel discussion about a new DRAM PHY Interface (DFI) standardization effort. Hosted by Denali, and moderated by Graham Prophet, Editor for EDN Europe, the panel members shared their thoughts on why standardizing the interface between a DDR/DDR2 memory controller and the associated PHY was important. Panel members included Badawi Dweik from ARM, Mark Gogolewski, CTO of Denali, Bryan Jones, Program Manager – IP Outsourcing, from Intel, Kimkinyona Fox from Rambus, and Navraj Nandra from Synopsys.
The main thing I took away from the discussion was that the DFI effort was focused primarily on the SoC market, where companies are purchasing design and verification IP for various system components, including memory controllers and PHYs. Currently, integrators have difficulty purchasing a PHY from a different vendor than their memory controller, or, if they have developed their own memory controller they have to pay extra for consulting time from companies such as Denali to help integrate their controller with a purchased PHY. Navraj Nandra from Synopsys made the case for standardization by comparing similar interfaces for technologies such as Ethernet and PCI-Express, noting that standard interfaces between digital and analog components made it easy to purchase IP when needed. I pointed out to Nandra that in the specific case of Ethernet, there was a push to integrate the analog components and that companies often modified the internal MII/GMII interfaces to suit their needs. Nandra responded that in the past it was more common to develop custom ASICs, and SoC developers frequently purchase IP instead of developing their own solutions.
Bryan Jones from Intel mentioned that as a buyer of IP, having standard interfaces was important from a verification perspective, making it easier to develop test suites that could be used across IP from different vendors instead of requiring his teams to develop custom verification environments each time a new IP module was purchased. Mark Gogolewski from Denali commented that his company currently sells a verification compliance suite for PCI-Express, and that it was conceivable one "could see a similar solution for DFI" from Denali in the future.
Would a standardized interface limit technological innovation for memory controller developers? Panelists uniformly said no, that would not be the case. The standard does not include timing parameters, and defines a common set of signals, including (according to Kimkinyona Fox from Rambus) control, address, update, data, and status information.
Towards the end of the session, I asked the panelists whether the DFI standard was strictly for DDR/DDR2 or if it could easily be extended to deal with other memory technologies such as FBDIMM. Apparently that question touched a nerve with Bryan Jones, who declined to comment on anything related to FBDIMM "at this time". Other panelists, including Badawi Dweik from ARM said that the standard probably could be adapted to FBDIMM if needed, but Navraj Nandra suggested that as FBDIMM was unlikely to be implemented in a SoC there was little chance it would be an "IP play" anytime soon.