Day 1 - ESL, URM, and SPIRIT
DRAM PHY Interface Panel Discussion

Day 2 – Security, Synopsys VMM, UCSI, and more!

Update June 12, 2007: Fixed out of date links to the Verilab blog.

First off, I've written up posts on the CoWare portion of the keynote, Cadence uRM, and Synopsys SystemVerilog support over on the Verilab blog.  Take a look when you get a chance! Today I had some time in the morning to check out a portion of the "Security and Trust in Ubiquitous Communications" session, specifically, the presentation on "Design Methods for Security and Trust" by Ingrid Verbauwhede and Patrick Schaumont.  It was fascinating and a bit scary to hear descriptions of how easy it is to crack encryption keys of many devices by simply analyzing the instantaneous power usage of a device or by monitoring electromagnetic radiation of a device.  Even worse, each proposed solution had additional drawbacks that made it susceptible to hacking.  Verbauwhede described the funny looks she gets from colleagues when she tells them she has covered her RFID-enabled Belgian passport with aluminum foil.  Frankly, I can't blame either her or her friends.

Next up for the morning was a discussion with HP. I went to the booth hoping to win a digital camera, but within a few moments had found a new best friend in Brian Lowe, Alliance Marketing Manager from the High Performance Computing Division at HP. Turns out, Brian markets high performance compute clusters that have been optimized to run EDA applications (also, check out this whitepaper) to computer chip design firms – just the sort of solution I've been looking for over the last couple of years!  I wrote about something similar in the context of grid computing (which HP also offers, but not in a form customized for EDA yet) back in August of 2005. Based on our discussion, I was able to deduce that there are at least a few large corporations using HP technology in this area (if anyone from HP cares to add details in the comment section or send them to me via email feel free and I'll update this info).

In my experience, building compute clusters to support EDA applications is a challenge; extracting peak performance out of a hodgepodge of components from different vendors can be more difficult than one might expect. Each system has its own unique performance characteristics, as do individual applications. Having a company like HP who is both a user of EDA applications and a system developer taking care of configuring a cluster is a great idea, and would be a good solution both for large corporations looking for a vendor to create clusters with thousands of nodes to a startup looking to quickly get something setup that "just works".

Over lunch, I attended the Doulos/Synopsys session on VMM and the new Register Abstraction Layer (RAL). I'm ramping up on the Synopsys SystemVerilog flow now, and it was helpful to have the opportunity to ask questions from experts on the topic. During the session I asked the Fabian Delguste from Synopsys whether the VMM would be open-sourced in the same fashion as the AVM library from Mentor. According to one of Fabian's colleagues in the room the VMM will be openly available and downloadable from the Synopsys website. It sounds like this was just announced in the last week or so, but I can't seem to find any reference to any announcement on the Synopsys website, and I couldn't determine where the VMM could be downloaded from. I've got some digging to do in this area.

Later in the afternoon I met with Dennis Brophy from Mentor Graphics, who is also Vice Chairman of Accellera.  I spent 30 minutes with Dennis talking about the new Unified Coverage Interoperability Standard (UCSI) working group. As soon as I get a copy of the presentation material he used while we were speaking I'll try to write up something in more detail about the topic.

Finally, after most everyone else had gone off to the DATE party (I wasn't sure if it would be worth 80 Euros to attend, so I didn't buy a ticket), I met up with Marouane Berrada from Texas Instruments here in Nice at the GreenSocs meeting. Marouane wrapped up the meeting with a presentation about his work on something he calls SystemPython. SystemPython is used by TI in France to create tests and configure a model written in SystemC with a Python frontend. SystemPython is a TI internal tool for now, but the intention is to release it into the public domain at some point. About 12-14 people were in attendance to hear the talk and also information about GreenSocs in general. GreenSocs has been around for about two and a half years and is a company based in the UK run and staffed entirely by Mark Burton. The goal of the company is to develop open source collateral and standardized methodologies for SystemC. Work is done by volunteers, university students, and by people who pay for Mark to develop IP for them that can later be released into the GreenSocs archive.

Tomorrow is "Space and Aeronautics Day" at DATE. I plan to attend a panel discussion hosted by Denali entitled "Bridging the Digital-Analog Domain for Memory System Design". I still haven't decided what else I'll take a look.

Friday is a day of tutorial sessions. There are a couple of options that look interesting - "UML for SoC and Embedded Systems Design" and "Secure Embedded Implementations". Ok, I'll be honest. The security tutorial sounds fascinating, but is less relevant to my day-to-day work. The UML has the potential to be far more useful, but also infinitely less exciting. I'm flying out of Nice late Friday afternoon, so I won't be able to attend the entire tutorial session, but should be able to hit most of whichever one I choose.

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