Mentor – Company of the Quarter?
DVCon 2007 Begins!

SystemVerilog vs. e

The DVCon sessions haven't yet begun, but I've been busy this morning snapping photos of the conference site and talking with some of the early arrivals. As I was setting up to listen to the Mentor tutorial on "Practical Applications of Mentor's Advanced Verification Methodology" I overheard Heath Chambers, president of HMC Design Verification out of New Mexico, speaking with Harry Foster from Mentor Graphics about some of the differences between e and SystemVerilog. I later approached Heath to see if he could clarify some of his comments.

Heath, a verification consultant since 2000, has a wide range of experience with the e language, and is also on the Basic and Enhanced SystemVerilog standards committees. I was pleasantly surprised to hear that there are e experts on the SystemVerilog standards committees. According to Heath, the main thing missing from SystemVerilog that can't easily be worked around is when inheritance. However, he says clients who have never used e have a difficult time understanding why AOP concepts are useful. To counter their arguments, Heath cites the difficulty software engineers faced 20 years ago when C++ came on the scene. He feels AOP adds a similarly useful layer of abstraction.

Separately, I asked Heath if there were any plans for adding introspection capabilities to SystemVerilog. Sadly, it appears the answer is no.

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