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March 2007

Mentor Says e/Vera On Decline… Cadence Says, Not Yet!

Update - March 1, 2007: Tom Fitzpatrick from Mentor Graphics has responded to Mike's comments.  For his response, please read Fitzpatrick on SystemVerilog.

Update - February 23, 2007: Just to let everyone know, I contacted Mentor for a rebuttal comment before publishing this story and have shared this material with them since.  If they or Synopsys care to comment for this story I will be more than happy to provide the space for them to do so.  And, as I mentioned at the end of this article, I would be happy to take a look at any existing 3rd-party numbers that may exist regarding the realities about SystemVerilog vs. e adoption rates.

At yesterday's AVM tutorial, Tom Fitzpatrick from Mentor Graphics made a statement that caught my attention.  He declared that "SystemC and SystemVerilog are the only two growing verification standards", and that e and Vera were on the decline.  In the interest of fairness I decided to check with Mike Stellfox, Principal Field Verification Methodologist for Cadence Design Systems.  This was his response:

"It is interesting that Tom would say that SystemVerilog and SystemC are the only two growing verification standards, and that e and Vera are losing ground – I'm sure it has nothing to do with the fact that he works for Mentor and they don't offer an e or Vera solution. The fact is that Specman/e usage continues to grow -  Specman added over 20 new customers logos in 2006, on top of the over 10 logos in 2005 (now nearly 400 customers using e), and Cadence estimates there are over 75,000,000 lines (and growing) of e code in use today. 

"Another interesting stat is that Cadence has recently expanded its presence in over 40 accounts where we displaced other simulators that had previously been working with Specman with the Incisive Enterprise Simulator (where Specman is built in).  It's interesting to note that a significant share of those displacements were Modelsim from Mentor.  Therefore we clearly see Specman/e market growth.  Cadence also sees strong SystemC growth, where I should point out that Cadence has been one of the EDA companies pioneering it for many years in the industry (long before Mentor jumped on the bandwagon). 

"The primary application where we see customers using SystemC is for Transaction Level Modeling (TLM) for early architecture exploration or providing a virtual prototype for early software development, and to a lesser extent for testbench development where we clearly see that most customers prefer e or SystemVerilog – especially when you look at creating constrained random, coverage driven testbenches.  Finally, we also see significant growth in the SystemVerilog market, especially given the fact that it is the newest and therefore is starting from a much smaller base than SystemC or e which are both widely adopted and have been in use for many years.  SystemVerilog is appealing to a lot of people who haven't really adopted constrained random coverage driven verification methodology since everyone is talking about it now.  However, I have found that most customers using e don't see any technical benefits for moving to SystemVerilog, and actually see some limitations and immaturity compared to their current solution (I have heard similar things from Vera customers). 

"The bottom line is that verification is a huge problem today and there will likely continue to be multiple languages required to solve the complete problems at hand.  Cadence is investing in providing the best multi-language simulation platform and methodology with a focus on seamless interoperability between the languages, and IP designed in e, SystemVerilog, or SystemC, so that customers can choose what they feel is best for the task at hand, and still have the capability to leverage IP that may be available in a different language."

It was interesting to see some numbers from Cadence on the current status of Specman usage.  Comments from Mentor and Synopsys (and anyone else for that matter), are definitely welcome!  I find it fascinating from and user perspective that Cadence, Synopsys, and Mentor can look at the verification landscape and come up with such dramatically different opinions.  I haven't seen any numbers from Mentor or Synopsys – does anyone know where to find third party data describing the HVL market?  If so, let me know!  I imagine a similar discussion will play out later today at the low-power panel hosted by Synopsys.  I'll be there, if for no other reason than to see if the attendees are able to stay in their seats, or if tempers will flare (as a few different people have suggested to me could occur).


Doulos at DVCon

This afternoon I had the pleasure of meeting Rob Hurley, CEO, and John Molyneux, President, of Doulos.  Doulos provides training courses and self-help materials on a variety of verification related topics including  SystemC, SystemVerilog, e, PSL, VHDL, Verilog, Perl and Tcl/Tk.    They've been providing training in Europe for several years.  Within the last few years they've been expanding into the US.  According to Rob, there are some interesting cultural differences between courses given in the US and in Europe. 

Continue reading "Doulos at DVCon" »

Veritools - Most Potential of DVCon Exhibits

Update February 23, 2007: Updates to quotes from Robert, added info on tool support.

Update February 22, 2007: (rephrased info from Robert about claims of tool capabilities)

So far, Robert has my vote as having potentially the most useful product being demoed at DVCon this year.  VeritoolsVerify has the ability to "independently evaluate assertions and coverage", according to Robert Schopmeyer, President of Veritools.  In addition, Robert claims the tool supports the same feature set as other competitors in this product category with improved stability and performance.

The list price of $4800/seat is quite reasonable, and if the demo is any indication, the tool has excellent performance.  The speed at which VeritoolsVerify was able to handle opening large waveform files, open schematic views in large designs, and trace back through levels of hierarchy was amazing.  Of course, it was only a demo.  According to Robert, the tool is supported on "Solaris 7, 8, 9 and 10 shortly and Linux, Redhat version 3 and 4 on 32 bit platforms and Redhat 3, and 4 on Opteron 64 bit platforms. These are the standard platforms today found in the EDA space... Windows-XP and NT are also supported."

Gabe Spotting!

  Gabe Moretti 
  Originally uploaded by brillianthue.

I caught Gabe wandering through the exhibition hall earlier this evening. Based on a discussion we had over lunch, he has every reason to smile.  Around 700 people registered to attend DVCon this year.  That's up from 500 last year.  I counted about 80 people in the AVM session this morning (rough estimate).  Not sure how many folks were in the other tutorials though.  It would be interesting to know how many people individual vendors were seeing stop by their booths.  Some of them were busy scanning (without asking in many cases, I might add) the DVCon badges of attendees, so they should have a good count (among other things).

Busy First Day at DVCon!

Wow - it's been a busy day so far.  I was hoping to be able to post up a few additional articles about some of the things going on this afternoon but I've spent the last 2 hours retyping/reorganizing my notes!  Since this morning when I attended Mentor's AVM tutorial, I also participated in the press luncheon with several notable figures (who I will describe in more detail as soon as I have time to write the material up into a post!).  However, I will say that Gary Smith from Gary Smith EDA was there, as well as Gabe Moretti (Gabe on EDA) and Peggy Aycinena (EDA Confidential).  I've read Gabe and Peggy's blogs in the past, so it was a real treat to get to meet them and to sit down with them and the rest of the group to talk about DVCon and the EDA industry.  I also had a run-in with Rob Hurley (CEO) and John Molyneux (President) of Doulos.  They were kind enough to tell me about what training materials they were getting the most interest in, and some cultural differences between training in the US and Europe. 

Now, I'm off to check out the exhibitions and get ready for the opening reception.  Tomorrow I hope to touch base again with Tom Fitzpatrick where I plan to ask him how the terms he uses to describe pre-silicon and post-silicon (verification|validation), among other things. 

As always, if there is something you're interested in hearing about let me know.

DVCon 2007 Begins!

  DVCon Exhibition Info 
  Originally uploaded by brillianthue.

Welcome to my coverage of DVCon 2007.  Hope you enjoy it!  Already I've met some interesting people and am preparing to sit in on the Mentor "Practical Applications of Mentor's Advanced Verification Methodology" presentation.  One interesting thing I learned from speaking with Heath Chambers, President of HMC Design Verification, is that Cliff Cummings from Sunburst Design won't be able to make it to DVCon this year due to a family emergency.  Heath will be manning Cliff's booth in his place.

SystemVerilog vs. e

The DVCon sessions haven't yet begun, but I've been busy this morning snapping photos of the conference site and talking with some of the early arrivals. As I was setting up to listen to the Mentor tutorial on "Practical Applications of Mentor's Advanced Verification Methodology" I overheard Heath Chambers, president of HMC Design Verification out of New Mexico, speaking with Harry Foster from Mentor Graphics about some of the differences between e and SystemVerilog. I later approached Heath to see if he could clarify some of his comments.

Heath, a verification consultant since 2000, has a wide range of experience with the e language, and is also on the Basic and Enhanced SystemVerilog standards committees. I was pleasantly surprised to hear that there are e experts on the SystemVerilog standards committees. According to Heath, the main thing missing from SystemVerilog that can't easily be worked around is when inheritance. However, he says clients who have never used e have a difficult time understanding why AOP concepts are useful. To counter their arguments, Heath cites the difficulty software engineers faced 20 years ago when C++ came on the scene. He feels AOP adds a similarly useful layer of abstraction.

Separately, I asked Heath if there were any plans for adding introspection capabilities to SystemVerilog. Sadly, it appears the answer is no.

Mentor – Company of the Quarter?


I arrived at the Doubletree Hotel in San Jose this evening.  As I was wandering around the hotel I started noticing some strange signs proclaiming Mentor Graphics as the "Company of the Quarter".  Sounds exciting, but what does it mean?  I checked with a woman at the front desk who explained that Mentor has booked the most rooms at the Doubletree over the last quarter, which entitles them to these nifty signs :-).  Could this be a conspiracy by Mentor to get extra advertising during DVCon?  Will there be a backlash from Synopsys and Cadence?  What about this week?  Who has booked the most rooms for DVCon?  Is that Mentor as well or will we have to augment these signs with "Company of the Week" and/or "Company of the Month" companion signage?


PS… My photography skills are not great, and my ability to create blog entries with photos is even worse.  Sorry!  I've also posted several photos from my first night in San Jose on Flickr.  Check them out!




[email protected]: “Hundreds of Cores: Verification Challenges of Tera-scale Computers”

Earlier this week I attended a presentation hosted by the Computer Engineering Research Center at The University of Texas at Austin and given by Brian Moore, Director of Validation Research in Intel's Microprocessor Technology Lab.  In "Hundreds of Cores: Verification Challenges of Tera-scale Computers" (sorry, haven't been able to find a link to the actual slides yet), Moore discussed recent advances in computer architecture and the challenges that validation teams will face as a result.  I was hoping he would delve into detail about the types of tools and techniques Intel was using to validate multi-core processors, and what his views were on whether those technologies would scale.  Instead, the discussion was more general, perhaps more focused on motivating the students in attendance.  Below, I'll summarize the talk and provide observations on where I would have liked to have learned more. 

Continue reading "[email protected]: “Hundreds of Cores: Verification Challenges of Tera-scale Computers”" »

Finally - Google Now Reporting Subscriber Statistics!

As some of you are probably aware, I use Feedburner to manage my RSS and email-based feed subscription services.  If you look at the top left corner of my site, you'll see a box showing the number of people subscribed Cool Verification.  The number fluctuates from day to day depending on whether people have their feed readers turned on or not.  The weekends are usually slow, but I've recently seen subscriber numbers up around 75-80 during the week.  This morning, I logged in to Feedburner to check my stats, and low and behold I had 109 subscribers yesterday!  That's a jump of 36% - which hasn't happened in a single day since perhaps the first day I started tracking feed subscriptions.  A little research through my stats showed the real cause - Google finally started reporting statistics for those subscribed to blogs via Google Reader or Google Personalized Homepage.  Google polls my feed each day on behalf of everyone who subscribes through those tools.  Previously, that would show up as one subscriber in my feed statistics.  Now, each time they poll my feed they provide a count of the number of people who have actually subscribed.  For details, check out Google's description.  The Feedburner description of the issue is also useful.

What do I use this info for?  Knowing how many people subscribe helps me understand whether what I'm writing is being widely read, and knowing which posts people are most interested in helps me know what topics to focus on.  For example, I'll be interested to see if anyone is especially interested in my upcoming coverage of DVCon (you are planning on reading my coverage next week, right?). 

I do want to thank everyone who reads Cool Verification on a regular basis.  Hopefully there are enough good nuggets of info passed on from time to time to make it worth your while.  As always, let me know if you've got suggestions for things you'd like to hear about.