DVCon Keynote – Gavrielov on Enterprise System Level Development
John Cooley, Recently Bathed, Hosts the Troublemakers Panel

News of Note From the Keynote

This morning Gabe Moretti kicked off the keynote with a brief overview of how the conference was going.  According to Gabe, 250 people attended 5 tutorial sessions on Wednesday.  The exhibitors' hall was full, and some exhibitors who wanted to reserve a space in the hall had to be turned away. Next year, the plan is to have a larger exhibitor floor. 

Tom Fitzpatrick from Mentor provided insight into the paper submission process.  99 papers were submitted this year.  33 were accepted.  5 tutorial sessions were submitted, and since all 5 were deemed worthy, a decision was made to have more tutorial sessions.

The schedule for the conference on Thursday included presentations on:

  • SystemVerilog for Design
  • Stimulus generation in SystemVerilog and SystemC
  • Formal verification
  • Real world verification case studies
  • A new track for "advances in research"

This year, the winner of the Best Paper award will receive $2000.  Unlike in previous years, there will only be one prize (previously, two papers were selected – one for design and one for verification).  Attendees should cast their vote for the best paper by 3pm Friday afternoon.

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