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March 2007

Writing Assertions

Yesterday I wrote up an overview of Tom Fitzpatrick's AVM tutorial last week at DVCon.  Today, I'm going to discuss Harry Foster's presentation on writing assertions.   If you want to know what assertions are and what they are for, check out Harry's book – Assertion Based Design.  If you don't have time to read the book, the concept behind assertions is relatively simple.  Basically, when someone designs a module, they often make a set of assumptions about the inputs and outputs of a module, legal state transitions, etc.  Those assumptions can be captured as a set of assertions. If the assertion is ever violated, the simulation will fail, allowing a user to easily trace a problem back to its source.  Assertions can also be used to provide functional coverage information for a design.

Continue reading "Writing Assertions" »


Mentor on AVM

Wednesday morning Tom Fitzpatrick kicked off Mentor Graphics' AVM tutorial entitled "Practical Applications of Mentor's Advanced Verification Methodology (AVM)" with an overview of Transaction Level Modeling (TLM) and the Advanced Verification Methodology (AVM) to a crowd of about 80 people.  I'd last seen Tom present info on Mentor's Questa a couple of years ago, and was interested to learn about the current status of the AVM.  The AVM is a methodology and an associated library meant for use with both SystemVerilog and SystemC.  So what is a methodology in the context of hardware verification?  According to Tom, a verification methodology should provide:

  • Automation
  • Observability
  • Controllability
  • Reusability
  • Measurability

By codifying verification best practices, Tom hopes to change the perception that "verification is an art form".  His view?  That verification is really more like "paint by numbers" and that a large portion of the work can be simplified down to a series of steps. 

Continue reading "Mentor on AVM" »


Closing Out the Conference

It's over!  DVCon 2007 is officially finished.  Tom closed out the conference by announcing the DVCon best paper award winners for this year.  He also announced that the final attendance was 710, a new record!  I'd like to thank Tom and the rest of the conference organizers for hosting a great event, and being available to help me out with info for stories over the course of the week. 

There are many technical challenges facing the EDA industry.  Though not everyone agrees on the details of how to move forward, the thing that struck me most about this conference is how everyone is converging on some common ideas.  For example, though there is heated debate about which low power standard should prevail, there is agreement about how to deal with low power (the two competing standards are apparently quite similar). 

Similarly, in the verification space there is starting to be a convergence of opinion that functional coverage, assertions, and constrained random testing are important.  Not everyone agrees on the exact tools and languages that should be used, but there are a lot of dedicated, hard working engineers on all sides of the problem whose goals are to get these problems solved.

Stay tuned - I've got more to say on the conference in the coming days.


DVCon 2007 Best Paper Awards

The voting was so close this year that two papers will split the $2000 prize.  The first winner is

"FEV’s Greatest Bloopers: False Positives in Formal Equivalence" by Erik Seligman, Joonyoung Kim Digital Enterprise Group, Intel Corporation, Hillsboro, OR.

The second first place winner is

"Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports" by Jonathan Bromley, Doulos Ltd, Ringwood, U.K.

Congrats to the winners!


Who Puts the 'Cool' in Cool Verification?

Ok, many of you have commented that my picture on Cool Verification looks nothing like me.  I'm not sure I understand... all I'm missing these days is a hat, sunglasses, and a beard... nothing that should make me look that different!  Take a look for yourself.  Here I am hanging out in the hallway of the DoubleTree hotel here in San Jose holding one of the conference signs (with a stern looking woman in a nearby chair giving Joe Hupcey and I an evil eye).  I didn't know Joe was a photography expert, but once I found out I was quick to ask him to help me take this shot. Thanks Joe!

We're coming up on the end of the conference.  The best paper announcement is in just about 20 minutes or so.  I'll be posting that live as soon as it is announced.  I've also got a huge stack of notes from the Mentor Graphics coverage panel this morning ("Blended Coverage: A Recipe for Success"), the Cadence lunch panel (" Does the Key to Verification Success Lie in the Language, Methodology, or Somewhere In-Between?"), and and from my interview with Mike Stellfox.  Both of the panels today  were excellent.  Kudos to Harry Foster and Mike Stellfox for putting together such interesting groups of people.


John Cooley, Recently Bathed, Hosts the Troublemakers Panel

Updated February 26, 2007: Switched out picture of John with a new and improved version.

Thursday morning after the keynote I had the opportunity to meet John Cooley of Deepchip fame.  If you've been at DVCon the last couple of days, you may have seen me lugging around my camera for just such an occasion.  I asked if I could snap a photo of John to go with my coverage of the keynote.  "Sure, no problem", said John, "but would you mind if I took a shower first?"  Fair enough, I said, so I waited until later in the afternoon to get this shot.

This particular photo of a sparkling clean John Cooley was taken after the Troublemakers' Panel.  I was hoping to write something up about the panel but it ended up (not surprisingly) being heavily focused on the backend tool flow.  Since I'm not an expert in that area I decided to sit back and enjoy the show.  The panelists were quite energetic.  I'm sure a couple of the other columnists (including Cooley) will write up the talk in great detail.  When they do I'll add the links here.  At one point, Brett Cline (AKA the SystemC Poster Boy) decided that enough was enough.  He had prepared a list of questions for John from a few of the other panelists.  Sadly, I wasn't fast enough getting my notebook out to catch them all, but I believe we're still waiting on the answer to this one:

Brett Cline: "So John - we haven't heard about your sheep for awhile...  did you guys break up?"

I'll be back online tomorrow with a final day of coverage of DVCon 2007.  I've still got quite a bit of material I haven't had time to write up yet from the last few days.  If you don't want to miss anything be sure to subscribe via email or RSS to save you from the trouble of having to check back here from time to time.


News of Note From the Keynote

This morning Gabe Moretti kicked off the keynote with a brief overview of how the conference was going.  According to Gabe, 250 people attended 5 tutorial sessions on Wednesday.  The exhibitors' hall was full, and some exhibitors who wanted to reserve a space in the hall had to be turned away. Next year, the plan is to have a larger exhibitor floor. 

Tom Fitzpatrick from Mentor provided insight into the paper submission process.  99 papers were submitted this year.  33 were accepted.  5 tutorial sessions were submitted, and since all 5 were deemed worthy, a decision was made to have more tutorial sessions.

The schedule for the conference on Thursday included presentations on:

  • SystemVerilog for Design
  • Stimulus generation in SystemVerilog and SystemC
  • Formal verification
  • Real world verification case studies
  • A new track for "advances in research"

This year, the winner of the Best Paper award will receive $2000.  Unlike in previous years, there will only be one prize (previously, two papers were selected – one for design and one for verification).  Attendees should cast their vote for the best paper by 3pm Friday afternoon.


DVCon Keynote – Gavrielov on Enterprise System Level Development


  Joe, Moshe, and Ric before the Keynote 
  Originally uploaded by brillianthue.

Moshe Gavrielov, General Manager and Executive Vice President of Cadence's Verification Division provided the keynote this morning at DVCon, entitled "Taking An Enterprise-Wide Approach to Next-generation System-level Development".  The overall theme of the talk was to demonstrate that verifying today's complex systems is an entirely different problem than that faced in the smaller designs of the past and that in order to solve this new problem, a more comprehensive solution is needed. 

Continue reading "DVCon Keynote – Gavrielov on Enterprise System Level Development" »


Get Exposed to SystemVerilog


  Get Exposed! 
  Originally uploaded by brillianthue.

Fliers were given to all of the attendees of the Low Power Panel over lunch today announcing the new SystemVerilog User's Group.  An interesting choice for the image for the front of the card, but the back contained a link to the site.  Jason Sprott, VP of Consulting with Verilab (my employer) is one of the members of the Steering Committee, as are Dennis Brophy and and Tom Fitzpatrick from Mentor, Cliff Cummings, Hans van der Schoot, Kevin Silver from Denali, and Jonathan Bromley from Doulos.  If you're interested sharing your SystemVerilog experiences with other users, head on over to the site and check it out!