As many of you know, DVCon is being held February 21-23 in San Jose. Looks like there will be an interesting technical program. The Wednesday tutorials will cover assertion-based verification, practical usage of the AVM and VMM SystemVerilog methodologies, formal verification, and SystemC. Thursday will be focused on SystemVerilog, SystemC, and physical layer verification, with the afternoon "bigwigs" panel, now renamed the "Troublemakers Panel" moderated by John Cooley.
I was excited to see that Jerry Vauk from AMD will be participating in the "Blended Coverage: A Recipe for Success" panel discussion moderated by Harry Foster from Mentor on Friday. I've worked with Jerry in the past, so it will be interested to hear his views on the topic. The rest of the day will include presentations on the SystemVerilog DPI, formal verification, advanced stimulus generation, low power design, and building reusable IP (among other things).
I am planning to attend DVCon and hope many of you will be there as well. In fact, I'd love to meet up with any of you who are readers of Cool Verification. If you're going to be in San Jose during the conference please send me an email (jl at coolverification dot com) and let me know!
Also, if my poor, depleted laptop battery can handle it, I'm going to try to post my thoughts on the conference live throughout each day on Cool Verification. If somehow that gets to be technically difficult I'll upload a report each evening. If there is any specific information that you'd like to hear about, drop me a line and I'll try my best to find out for you!