I'm on the "Verification Horizons" mailing list from Mentor Graphics. Today, one of the items caught my attention. It was a link to an article entitled It's a Matter of Style: SystemVerilog for the e User. The article describes how, given the lack of AOP in SystemVerilog, a user can implement some of the features available in Specman. Technically speaking, they are exactly correct. Anyone using SystemVerilog (especially if you're used to using e) should read the article and follow the recommendations. However, the conclusions they draw - namely that there is either no difference between SystemVerilog and e or that SystemVerilog is inherently better - are completely false!
I can't believe that anyone at Mentor has ever written a serious testbench in e. The article deserves a point-by-point analysis which I don't have time to write up at the moment. I'll give it a shot over the next week or two. In the meantime, check out the article, and let me know what you think!