I just noticed that someone hit Cool Verification using the Google Search "tips for building verilog verification environment". Here's my tip - don't do it! Ok, you'll have to do it a little bit but if you're thinking of building an entire environment from scratch exclusively in Verilog you're insane. Thinking of adding a little C/C++ through the PLI to spice things up? For your own sanity and to prevent yourself from having a day like this one you might want to reconsider.