Back in August, Denali launched Blueprint, a tool to automate "the generation and management of the hundreds, and often thousands, of control registers used in complex chip designs as a source for efficiency improvements in system-on-chip (SoC) design."
According to Denali, "Blueprint is used by chip design teams to automate the creation and
management of control registers, and all related models, design views
and documentation. From a register description language (RDL) input,
Blueprint generates views for hardware and software development,
verification, and documentation. Supported output formats include
Verilog, C, C++, OpenVera, e, OVL, Frame, HTML, SPIRIT-compatible XML,
MS-Word and more."
I haven't had the opportunity to try Blueprint yet, but I've used similar tools at other companies. A common concern among engineers who are introduced to such a tool is that using the same code as a starting point for both the design and verification leads to both environments having the same functionality, implying they will also have the same errors.