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Newsflash: Cooley Doesn't Like HVLs

Cooley just published his yearly verification survey, proving once again that there really is a general lack of understanding in the design community about what it means to be a verification engineer.  Don't get me wrong... Cooley seems to know what he's talking about when it comes to back-end design issues.  However, I shudder every time I read an ESNUG post describing how awful HVLs are, and how everyone should use Perl and C for building complex test environments.  It seems many posting to DeepChip these days are excited about SystemVerilog, down on e, ambivalent about Vera, and love their Verilog, C, and Perl testbenches!

Here are some numbers from Cooley's report:

Subject: the Future of Specman "e" and Vera

FUTURE DOOM -- Just like 2004, there's no way to sugar coat it in 2005; the majority of engineers yet again see no future for Specman "e" nor Vera.

2004 - "Where do you think specialty functional verification languages be in 5 years?

Dead or a growing part of the chip verification process?"

             Dead :  ######################################### 81%

          Growing :  ########## 19%

2005 - "Where do you think specialty functional verification languages be in 5 years? 

Dead or a growing part of the chip verification process?"

             Dead :  ####################################### 78%

          Growing :  ########### 22%

Of course there are always a few fanatics faithful to the old regime, but the masses seem to see System Verilog as the future heir to the verification crown.

Gee, I'm glad to hear that the "majority of engineers yet again see no future for Specman [nor] Vera."  Why do the so-called majority of engineers think this?  There are likely several reasons.

Of engineers that don't believe in HVLs, I estimate that most of them either currently use Verilog or VHDL testbenches, or if they have used e or Vera they have never invested the time and money into training themselves on how to use the tools correctly.  How can I say this with such certainty?  Because I've written testbenches using e, Vera, and SystemC/SCV.  I've also seen the tools used at many different companies.  Without proper training, most people with a hardware background are likely to write testbenches in any of the above languages as if they were writing in an HDL.  Need more proof?  Check out this comment from the survey: 

http://www.deepchip.com/items/dvcon05-05.html
Both 'e' and 'Vera' were -invented- to create a new market segment for EDA sales.  I have seen features of both and other than the so-called 'random' number generation routines provided by the languages, there isn't anything significant that you cannot do with Verilog and C/PLI.

In fact, both (at least 2+ years ago) slowed -down- our simulations. Maintaining 2 language environment (in an eval we did with Vera) was a nightmare; not to mention the expertise required for 2 languages. We stuck to Verilog/C and did VERY WELL.

      - [ An Anon Engineer ]

Quite a lot of software these days is written in Java or C++.  If the general software community has embraced OOP and AOP (think AspectJ) design methodologies it would stand to reason that the same principles could be applied to the verification problem.  Part of the problem has to do with where verification engineers come from. (What, you didn't have this discussion with your mom and dad when you were growing up?)  Many times verification engineers are designers who were retasked to create a test environment.  Since their background is hardware, they think about the problem from a hardware perspective.  If instead verification engineers were hired from a pool of talented software engineers who also happened to know hardware, you would never have to have a conversation about the benefits of using object oriented design principles vs. a procedural approach.

Another reason many people feel that ultimately there will be an end to specialized verification languages is the believe that SystemVerilog with it's all encompassing scope will make HVL's obsolete.  I hate to break it to you, but the verification part of SV might as well be considered a specialized verification language (especially since it's in large part based on Vera).  So, not only do you still have a specialized verification language, but now you have to live with some of the arcane syntactical sugar of Verilog (begin/end instead of {}, as an example).  People who were happy with their Verilog testbenches will be just as happy with their SV testbenches.  Will they be more successful than they were before?  Not likely.  The real power of SV, Vera, or Specman comes in taking your verification environment to the next level where OOP and AOP programming techniques can be used.

There's an old saying - "You can lead a horse to water but you can't make it drink."   All I can say is Cooley and many of the folks who responded to his survey must be awfully thirsty by now!

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