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eRM for SystemVerilog? The Devil Better Get Out His Earmuffs!

It's been a long time coming, but it looks like the e Reuse Methodology is making the jump to SystemVerilog:

Link: EETimes.com - DESIGN LANGUAGES: Verisity verification tools tuned for SystemVerilog.

According to EETimes.com, Cadence will be announcing verification methodology and process automation software support for SystemVerilog.  I'm a big fan of eRM.  It enables engineers to share verification IP both internally and externally without having to worry about someone not understanding the way they've packaged their code.  It also promotes good software design practices. 

It will be interesting to see how eRM fits in with SystemVerilog given the absence of AOP support in SystemVerilog.  It now appears that each of the three major EDA vendors has announced their own separate SV reuse methodology.  One issue is that the nice thing about having a methodology is having it commonly used throughout the industry.  If each vendor goes off in their own direction, it seems likely that people could get locked into a particular vendor simply to ensure their favorite libraries are available. 

Another part of the announcement deals with what looks to be vManager support for SystemVerilog.  I spent a few months using vManager earlier this year, and though Verisity was still working out the kinks at the time, it's great to see someone focusing on creating a standardized way for people to deal with the enormous volume of information generated from a constrained random testbench using functional coverage.  It's probably safe to say that most big companies have created their own set of scripts, databases, and web pages to try to manage simulation data and link everything together with a verification plan.  It's a shame there isn't more of an open source atmosphere in the verification community that would allow all of the good work done around the world to be shared.  In the absence of that, we'll just have to rely on the big three to keep things moving in the right direction.

At the moment Synopsys seems to be in the driver's seat when it comes to SystemVerilog.  Perhaps this move by Cadence will start to turn the tide in the other direction.  Either way, it can only be good for everyone to see so much energy being put into making life easier for verification engineers.

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