eRM for SystemVerilog? The Devil Better Get Out His Earmuffs!
Newsflash: Cooley Doesn't Like HVLs

Can't... Take... Much... More... Of... This!

My wife and I have been busy over the last couple of months trying to get our house cleaned up.  It's been a royal pain - we've only lived in the house for < 4 years and we've still chucked several bags of trash each weekend.  The whole process has been ripe for a blog post comparing messy houses with messy verification environments.  I was able to spend some time building up a mind map about it using Freemind this evening (thank goodness for the extra hour last night thanks to the end of daylight savings time).  I've also spent time over the past week trying to compose my thoughts about John Cooley's verification census.  And then there was that unfortunate incident earlier this week where I started some "minor" household repairs that are going to end up needing the assistance of a construction professional... Doh!  Oh yeah, and have any of you spent any time creating UML descriptions of your verification environments using tools like Umbrello or MonoUML

What's the moral of the story?  You might see a slowdown in the frequency of articles over the next week or so... rest assured I'm still here, just a bit busier than usual!

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